10/30 國際電機電子工程師學會2007亞太地區電腦會議(Tencon 2007)

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IEEE TENCON 2007  Taipei International Convention Center  10/30~11/2

Intelligent Information Communication Technologies for Better Human Life

About TENCON

IEEE TENCON 2007 will be held in Taipei, Taiwan. TENCON is an international technical conference sponsored by IEEE Region 10 to provide an international forum for technical presentations, discussions and interactions. The conference will feature world-class keynote speech, tutorials, exhibits, and lectures and posters sessions. TENCON 2007 will seek papers in different aspects of recent technological breakthroughs in the related fields to evolve convergence in technologies and people.

http://conf.ncku.edu.tw/tencon2007/

Keynote Speaker

Title：Research Challenges in High Performance VLSI/SoC Circuits and Systems

Professor Eby G. Friedman
Department of Electrical and Computer Engineering
University of Rochester, USA

Abstract

The presentation is composed of three parts. The initial topic will review the fundamental trends specific to high speed, high complexity integrated systems, emphasizing many of the primary issues that constrain existing and futuredigital and mixed-signal integrated systems-on-chip. These issues will be discussed in terms of the evolving criteria that
affect the VLSI/SoC design and synthesis process.
The second portion of the presentation will review specific research problems and challenges that drive our current and near-term research focus in the field of VLSI/SoC design. Effort will be made to distinguish between local vs. global research problems. Thus, topics such as dual Vt CMOS circuits and on-chip interconnect noise, determined by the local nature of the circuit structures, will be compared and contrasted with research problems that focus on the global nature of VLSI-based systems-on-chip such
synchronization and clock and power distribution networks.
Finally, specific results recently developed at the presenter's research laboratory in response to these challenges will be reviewed and summarized. Time and interest permitting, different research results will be described in the areas of power distribution networks for high speed, high complexity applications, clock tree synthesis for increased tolerance to delay uncertainty, resonant clocking design methodologies, 3-D design methodologies and algorithms, design methodologies for placing on-chip decoupling capacitors, low swing dual Vt domino and adaptive body biasing
circuit techniques for low power applications, shielding methodologies for high speed interconnect, on-chip DC-DC conversion, substrate coupling in mixed-signal systems, and design methodologies for inductive interconnect.