Month+ ?3 t j; K0 w | Topic9 a* m1 J3 ?2 l# K+ r* B |
January. z7 K. E- k; e% I# S1 e$ l9 ` | • Parasitics & Parasitic Extraction |
February | • Verification Methodologies & Tools • CAE/CAD Tools for FPGAs |
March | • Configurable & Reconfigurable Processors |
April' ~6 A$ _0 t9 V- P) d$ S | • Hardware/Software Co-Design# x, G4 H# f- [3 e, Y/ g+ W8 w k • On-chip Interconnect, Network on chip (NoC) 9 ~1 q& k0 C' X9 j' e6 J) X; p8 I; J( { |
May | • Electronic System Level Design (ESL) |
June! d% W8 R0 t% g0 Y, `9 F | • Timing Analysis, Closure, & Sign-off1 [7 [. o! n: ?* a! _8 I* o • Low-power Design Methodologies & Tools |
July | • FPGAs in DSP Applications0 j8 m0 l" B) t9 W |
August | • Formal Verification Methodologies & Tools |
September | • Structured ASICs & FPGA-to-ASIC Conversion* x9 C, z) R5 s; d- b+ w. `0 l • Design-for Manufacturing/Yield (DFM & DFY) * o# H" g8 J! I9 m1 q6 L |
October | • ATPG, BIST & DFT `* y$ F0 P& v) c |
November | • Physical Design (Partitioning, Floorplanning & Placement, Routing, Optimization)% f, ^: w9 }( o9 y • Device/Circuit Modeling & Simulation! I0 L# K0 t x n3 Y% T/ i1 f |
December% u8 W- m. c7 e& K( L& V2 w8 m | • Analog & Mixed-Signal Design6 \+ w/ G' Y8 P/ _4 H6 _, k' r |
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