標題: 請問由Verilog code到IC layout 需要哪些軟體 [打印本頁] 作者: leesg 時間: 2009-5-18 03:38 PM 標題: 請問由Verilog code到IC layout 需要哪些軟體 問題, 已完成 Verilog code 設計, 模擬(ModelSim)1 R3 p( Y+ D; n( ^+ H
想要用軟體直接 run 到 IC Layout 產生 die photo, / i: G9 t, L& H+ W要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)# J3 I7 |5 B9 M8 \+ L1 S' t3 `% k
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design compiler + Astro ?3 R5 L! Y& @5 ~
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synopsys IC compiler ?/ h g4 i4 C' {0 x; s
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cadnece virtuso ?作者: lee100 時間: 2009-5-19 10:30 AM
Synopsys R2G flow ) Z% Y p, n9 d8 m& v6 h' [: `1. rtl simulation by vcs # f" W z% [9 r2. synthesis by design compiler ultra with dc/dct mode* o v: G% ^+ j, D
3. dft insertion by dft compiler$ a& w1 z/ i8 c* b# R
4. jtag insertion by bsd compiler0 \* k; E6 t i. N" ]: i
5. ICG insertion by power compiler 5 {! @: k/ d; g& O- ?6. pre/post-layout STA by prime time 6 r' m- @, _+ k: p! i5 l) Y/ t7. pre/post-layout power analysis by prime time px 4 L, k" _4 T, _3 a4 d6 q A. ]2 ~8. PnR by IC compiler1 S( p; D+ @; [& f' e
9. post-layout SI analysis by prime time si: R3 v% r3 } o0 ?4 y8 [
10. post-layout simulation by vcs作者: putechen 時間: 2009-9-7 11:32 AM
sometimes ,star-RCXT is necessary.just for layout PEX.作者: yytseng 時間: 2009-9-28 09:44 PM
after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.2 T7 g' Q/ x* \! @
clean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.作者: ejean 時間: 2009-10-9 05:16 PM
1. magma is another solution ( o5 h. J ?5 G0 T* m2. Astro from synopsys $ @1 S8 k2 @# E. m7 `3. FirstEncounter from Cadence 9 o) r# y" W. m+ G' b" L* L. o4 b% d& Q- s$ Q
All with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.作者: ilovepachaya 時間: 2010-9-16 09:18 AM
私心推薦APR使用IC Compiler 效果很好