標題: 關於電阻的設計 [打印本頁] 作者: squirrel316 時間: 2009-5-22 12:17 PM 標題: 關於電阻的設計 在CMOS製程中' _) @* B: {* Y5 F" l
大致上可以知道說阻值等於sheet resistance*(L/W) 6 E& |0 m2 C# O4 l不過我有個問題就是L跟W值的選取. D- A, {: `+ W' M
假設我要讓L/W=2; \; N' t' n F% {, @ X
我可以有很多種選擇 像是2u/1u 4u/2u ...等8 I s/ \- v& r- f' @3 L: I
那請問一下這幾種選擇除了雜散電容造成的影響之外 5 P" S* @6 N+ K/ ^還會有什麼影響! h' \5 Q% c% J0 d' Y8 x* n
謝謝指教作者: seanyang1337 時間: 2009-5-22 03:30 PM
Dear squirrel316,4 l- T$ H. Q! }1 _+ z1 v F& R3 R
Basicly, the W should big enought and has a low bond(usually 2u for above 0.35um). 9 D$ Y2 d; H& c0 xIf you using too small scale like 1um, the accuracy will be very poor.1 {8 q) i6 H6 U1 p
And it should be considered the eatch value.! l' n1 E+ k7 A g+ \/ z
As a reference, the foundry resistor test key, was measured by 10u/10u or larger.