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標題: LVS問題 望大大指點 [打印本頁]

作者: xjyy    時間: 2009-5-26 10:45 PM
標題: LVS問題 望大大指點
使用LEdit90的LVS時,顯示This file is Binary.LVS can not perform iteration.無法進行對比,這是怎麼回事呀
作者: m851055    時間: 2009-5-27 07:43 PM
是比對檔案中路徑的問題,若有需要詳細說明把netlist PO上來................
作者: xjyy    時間: 2009-5-27 09:12 PM
標題: 回復 2# 的帖子
原理圖
  ?: Z8 y0 y2 p. r* SPICE netlist written by S-Edit Win32 7.03
& v. p( P( v. A' t# s* Written on May 27, 2009 at 16:57:24
7 z$ n0 C) A$ l* Waveform probing commands
% H% R  H2 b- U& J0 q.probe8 |2 F. T- I$ O8 B
.options probefilename="G:\tanner\Nand2_1.dat"% J& {; [9 q, I' ]2 g
+ probesdbfile="G:\與非門2.sdb"* ^8 j( Q0 r/ M6 c" }6 j
+ probetopmodule="Nand2"
/ j7 X/ \5 R! q; f  L* Main circuit: Nand2
5 x+ ]1 _- O6 P, l1 M' h8 t( kM1 OUT A N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u ' n/ T/ r! p3 |
M2 Gnd B N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u 6 i6 x( s% K- n6 k; P1 m5 E
M3 OUT A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
4 @& q- B3 |; e% nM4 OUT B Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u+ Z+ f/ P. G/ J+ E$ a
* End of main circuit: Nand2
作者: xjyy    時間: 2009-5-27 09:12 PM
版圖
- }' w/ _$ a# @8 N6 ?+ R* Circuit Extracted by Tanner Research's L-Edit Version 9.00 / Extract Version 9.00 ;! H. o+ x( d2 V$ D8 C
* TDB File:  G:\tanner\Nand2.tdb9 e9 T) V2 A9 O. \+ \
* Cell:  Nand2        Version 1.07
4 d/ ?3 F( ]( `7 P* Extract Definition File:  G:\lights.ext7 c# X1 a9 m+ E
* Extract Date and Time:  05/25/2009 - 15:051 G: H+ m$ e+ r! L% ?
* Warning:  Layers with Unassigned AREA Capacitance.
, V- h* Y2 i/ N3 M( ^2 N8 J# J6 c*   <N Well Resistor ID>
/ @2 C. h' r6 }' \*   <Poly Resistor ID>5 }6 ~6 F, n7 a2 i7 n8 n  z
*   <Poly2 Resistor ID>2 o! v  V1 |' l+ z: v3 m9 V
*   <N Diff Resistor ID>0 C$ R2 j+ Z+ m9 z, ~0 e' P' |
*   <P Diff Resistor ID>; W$ `3 y' M# t$ Z" K  F
*   <P Base Resistor ID>
! V5 Q" G) y# y# `, M5 f: t* Warning:  Layers with Unassigned FRINGE Capacitance.* x0 z' c- E2 {4 w/ o
*   <N Well Resistor ID>
" a0 q% W4 Z: J) g. H0 a8 k% U*   <Poly Resistor ID>. X0 k+ L7 z, f/ i
*   <Poly2 Resistor ID>/ k! W- M  k4 }; o" G
*   <N Diff Resistor ID>
% \  g- T1 \/ l/ U% E*   <P Diff Resistor ID>0 q9 s, e0 h- m6 P" k
*   <P Base Resistor ID>
$ ^: U- R! r: m3 ?*   <Pad Comment>& D" B$ e$ f+ H. h/ N5 M; d
*   <Poly1-Poly2 Capacitor ID>1 F7 H8 w$ s; _* W
* Warning:  Layers with Zero Resistance.
  G$ l* D8 o, W*   <NMOS Capacitor ID>
! b- j5 c' D. H5 W! Q1 s*   <PMOS Capacitor ID>
6 j) {. N2 D! g7 W6 q*   <Pad Comment>
: t, E% `& y6 V7 V  n( a2 R, x) T*   <Poly1-Poly2 Capacitor ID>7 S$ {$ H7 N5 y! {. ]
& v8 p. ]5 A5 ^4 x
* NODE NAME ALIASES. H- O9 c, O( X
*       1 = B (12,-14)2 X1 S% q# N2 m, b" r
*       2 = A (-16,-18): A; E  x6 ]! ]5 Z/ R; r2 F
*       3 = OUT (-2,-21). b( i5 \+ s; k3 T7 z: V( D
*       4 = GND (-30,-35)6 `. E2 }5 @# S: T1 C' M& S
*       5 = Vdd (-32,14)- R3 n( k; ^5 I; y7 q3 J
M1 Vdd B OUT Vdd PMOS L=2u W=6u 0 L, m( j, w) N: G/ Q) H" o: q
* M1 DRAIN GATE SOURCE BULK (3 -3 5 3)
" V& {" e. L" i& g' NM2 OUT A Vdd Vdd PMOS L=2u W=6u
! Q3 F4 H6 D! z/ @$ V# Q3 u8 E* M2 DRAIN GATE SOURCE BULK (-5 -3 -3 3) # L% t/ ?/ p; C1 o
M3 OUT B 6 GND NMOS L=2u W=6u
: r$ C8 d1 g$ _4 M* M3 DRAIN GATE SOURCE BULK (3 -31 5 -25) 7 q; N' t  {0 O9 b
M4 6 A GND GND NMOS L=2u W=6u 3 c% F8 ~2 Q+ I- s( y" o% _; q5 `- e
* M4 DRAIN GATE SOURCE BULK (-5 -31 -3 -25)
% p, P5 I8 v  U+ A# d+ \* Total Nodes: 6
" B" d: s7 B7 T4 K* Total Elements: 4
3 d' f+ J& E- R" r/ [  H1 A, r( o( |! R8 ~* Total Number of Shorted Elements not written to the SPICE file: 0
) B6 ^5 b+ k4 S* k4 C7 s* Extract Elapsed Time: 0 seconds8 L1 p3 R% x# N1 ]- b6 l
.END
作者: m851055    時間: 2009-5-30 10:14 PM
與非門2 files name改為英文名稱.......................
作者: xjyy    時間: 2009-6-2 02:16 AM
我宅了一周 沒想到栽在路徑上  萬分感謝 !!!!!!!!!!




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