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標題: 11/19-20 Semiconductor Manufacturing Forum 2009 [打印本頁]

作者: chip123 時間: 2009-10-21 05:58 PM
標題: 11/19-20 Semiconductor Manufacturing Forum 2009
由台灣半導體產業協會主辦之「2009半導體製造技術論壇Semiconductor Manufacturing Forum 2009」將於11/19-20於新竹交通大學舉行，會中邀請關於Thin Film、Asembly, Packaging & Testing、Diffusion、Design, Reliability & Testing、Litho與Etching等專家對未來趨勢與新技術進行專題演講，是半導體專業人士不可錯過的一場盛會，即日起開始報名，歡迎各界踴躍參加。

2009/11/19-20 National Chiao Tung University Library International Conference Hall
交通大學浩然國際會議廳

Agenda 議程
Session 1: Thin Film (11/19 13:20-16:20)

' _+ q7 y( w4 w$ @1 Y* r5 j	Topic	Speaker
13:20-14:00 . @( P3 r. Y( o0 g/ a Z	Engineering Slurry for Copper Chemical Mechanical Polishing " e4 ^+ k) i: I/ W1 _' Z7 U3 t	Dr. Song-Yuan Chang / , Z0 E) f: n7 a, H CTO& senior VP, UWiZ , H3 ~5 ^! q8 m( u7 i, P, d8 V( GTechnology
14:00-14:40/ X/ b! Z. p1 z9 z j9 f	Tailoring CMP Consumable Sets To Meet the Increasing Demands Of IC Device Manufacturing For Advanced Nodes	Dr. Fred Sun / Cabot9 A6 h( E6 o$ e7 s$ T6 a
14:40-15:00 % ]& [' W: K; k, E5 F/ }	Break , {1 B- S6 M3 v G: k9 _	0 F6 g; }1 S7 k& _: C
15:00-15:40 7 t& \/ U9 m% v6 D1 {! Z	? / u' a$ g* a0 m& {1 \9 Z3 i' D9 w# a. I	Apllied Materials1 Z% O4 e' r0 g( i/ H1 s# d
15:40-16:20 # ~& r# `" ^! O. B# K" w	CMP Fundamentals and Implications for Consumables Design Q( \! m% A. M	Ms. Kate Kao/ Marketing Manager Dow chemical1 B$ v5 ?1 K7 X- {4 y

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作者: chip123 時間: 2009-10-21 05:59 PM
Session 2: Assembly, Packaging & Testing (11/19 13:20-16:20)

7 k6 O& z% Y6 u; ^) r( Q/ d	Topic+ Z) {/ ~* y; p8 G# s/ v8 Z# g2 f: G	Speaker 0 h" e, c1 K4 H8 y+ _
13:20-14:00 : N2 Q$ q4 z) U9 a0 D n% I	Sip Assembly technology?2 G+ l$ L* m$ U2 z	Dr. KC Yee/ VP, ASE) L2 @8 l# [: y
14:00-14:40. [) m! L9 l5 J6 \|	Assembly trend from perspective+ o; z% h8 U3 C4 n4 w	邱世冠資深經理/矽品( ^5 p/ B6 [* G* m 前瞻科技中心 ( i' h- j( C9 Q5 u
14:40-15:00 * t$ d( x) k" g	Break & L, i. u- n# I2 z+ v	' X; K, h( I# Y N
15:00-15:406 {% S, z+ ?( {9 ^' E	The Paradise of Cost-Effective Wafer Probing Technology ) S' j8 p1 X6 C) z	Dr. CCNi / Associate Director , KYEC/ v U$ k! P: a; K( `# W% G3 `
15:40-16:200 @5 i5 o( w0 I) s b, Y	RF SOC /Sip? * Z5 Y, x# N+ ]9 T' d5 F9 i	Verigy ; C- }0 ^4 m, A d% D' m

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作者: chip123 時間: 2009-10-21 05:59 PM
Session 3: Design, Reliability & Testing

4 E# Q3 a6 F; V; w6 x	Topic 9 S$ [* \0 k* `' H; Q$ I	Speaker [% ^$ E# u0 }& I" x8 T
9:00-9:40* s5 @$ t7 Y! e+ q7 E& B- _	Design Trend? 9 [; \|/ ` W( u& P- H4 g	Marketing VP, Dr. Chiang Alchip" j' u F, z( M4 \|6 ]
9:40-10:205 w x3 x0 ?& \|	Charged-Device-Model (CDM) ESD Protection in CMOS Integrated Circuits 2 X q- j* n$ ?. m& D7 V, T0 H* E	Prof. Ming-Dou Ker / I-Shou Universit 2 M5 e7 W9 m* Y2 p9 j. {) B1 B
10:20-10:40 5 i& y. O% N* n5 i1 `4 W	Break 6 R- t! u. G0 W" I# U4 \	; A( P9 X# f/ p3 T( y, E* d
10:40-11:20 y. _) G2 F, p/ H8 s/ P	Parametric Test Challenges of the Next Process Frontier , G; W2 N K" \* g2 [' z	Ms. Flory Tsai / agilent ! H/ ^+ a% A4 C+ l2 L7 b
11:20-12:00 # t3 r+ I& P9 i7 }; o }8 r9 V	Recent Development Work and Trend for Semiconductor Device Characterization 5 W- S7 I7 L: d1 C: S	AL Feng / 專案經理 / Keithley Taiwan . H/ M! D, o5 r# \6 D! H2 P) n9 g

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作者: chip123 時間: 2009-10-21 06:01 PM
Session 4: Diffusion

' R# o! l$ P' D. ]* D, a% T2 K: t	Topic $ X, s: o' S4 U8 u' e& K6 I	Speaker , b0 s8 C" d0 `1 X
9:00-9:40 5 p# [" v7 L4 a% o2 Q9 t) i) g3 B	Surface Preparation process control requirement to support CMOS scaling into 22nm ) ^* J* G* ?! O! C# }# O	Dr. Scott Becker/ Vice President, FSI / n& _/ _: F+ ?0 x
9:40-10:20 - U9 _' f p& j: ]	Wafer techincal roadmap and application for advanced or special proces - }, m) V8 \ L+ \|) W	MEMC ! T! h& d( Y0 E% q
10:20-10:40 " @/ B* F- S. s	Break & C6 B) `7 }, N6 w4 r	1 ^% ~# H9 K4 k: K( U7 k
10:40-11:204 T: j) ?3 K4 k* H	$ K$ \|' r# i- F1 M6 X4 \|; N* Z	$ b4 O/ @2 \& o4 b- e+ ~/ X

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作者: chip123 時間: 2009-10-21 06:02 PM
Session 5: Litho

" @1 s7 A6 F$ ?. @# [1 \|! P8 I3 G( f	Topic* W9 C4 Z8 N7 o. [% ]	Speaker 7 Z; m* q. @. s
13:20-14:00 9 U; W) {9 m& T( Z	Photomask technology for 32/22nm and beyond 0 N5 E9 o0 N) I. m, b% N	Dr. Hiroaki Morimoto/Senior General Manager,$ t5 ]8 v3 i, l7 k- Y/ s Toppan Printing! z- q9 b" q; L: w9 Y
14:00-14:400 U- Y m* l/ K+ c	2 N3 A; S: ^6 k Implant Resists for Advanced Node Applications / g% J8 f3 Z m2 _5 b	Mr. Yoshiro Yamamoto/ & T0 R' r8 u- \: D3 hDUV RD mamager, DOW% w/ T2 B4 V1 r/ v" A, ]% O# } ) p8 H. w1 R# L$ rSemiconductor Technology 8 \% L6 H( _4 T
14:40-15:00: H1 T1 k8 h1 A9 v5 W( b	Break % K' v% v" e$ P9 m3 j2 }' ^1 ^
15:00-15:40. j3 Z, x* B6 v& I	State-Of-The-Art Development of BARC Material " x$ ]. i% B) A! O. u: e2 @	Brewer Science * d) Y- K3 T4 i F0 s; M/ Y
15:40-16:20 $ y5 x6 y7 }8 m8 Y' V8 J	The Future Trend for Next Generation Lithography 4 I+ W8 o6 M$ p$ }) s- q: q1 x	ASML6 ~6 B8 d/ c. y; S1 g
16:20-17:00/ q& K( [, i$ p& \% v1 u( x% A	Future Trend of Track Technology 3 @* w0 I7 l) B' M7 Z; o	TEL+ Y W6 O5 _, }* u) d5 c: v

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作者: chip123 時間: 2009-10-21 06:02 PM
Session 6: Etching

; x$ }" Z/ \4 ~+ y. h! t0 O	Topic' J( q' h. L i( [	Speaker, l' {' O) L* j4 m& F
13:20-14:003 k3 \" Z6 M0 L3 K3 U- ~. o	The Advantages of real-time wet process monitoring by multi-channel, in-line NIR analyzer 3 G& ^4 K- s) L" X; U4 J/ Q. P0 i3 L3 F	Mr. Shay Tina / CI Semi , Director of Sales k u; R+ ^) [4 F6 h4 j7 {0 Q
14:00-14:40 , ~* I% E/ B6 r8 P9 O1 W- u+ {2 Q	Green Chemistry for current technology and beyond. c9 v1 _9 i! ]	Mr. Elvis Sheen / Mallinckrodt Baker, Senior Manager/ E0 ^6 U" m. b# x: ^) ?% L3 Z$ k
14:40-15:003 k5 }+ E7 \|" T& y3 X( n! J	Break4 R% L) G1 H y. x( c! X/ j	' r T6 D& i. M7 F& ]& V. z
15:00-15:400 B* \| R9 T7 q' w s! X7 \|	Post-etch residue removal for advanced copper low-k device & L6 g, v. x6 f4 E5 Y! ]	Dr. Hisashi Takeda / EKC Technology, DuPont ; m5 g2 z1 c9 k$ E; `
15:40-16:20 0 q' q/ L3 I! i# C- Q' U	Edge Die Yield Improvement with Immersion Lithography Defectivity Control by Bevel Etch Clean * b* p1 v& G4 z \0 t9 i9 v) i	Lam Research+ C& ^ f* z3 j4 i1 N. S4 ]) a* b
16:20-17:00& j. {* J2 _* ?& r0 x	Improved Control of Through-Silicon Via Profiles for Advanced Packaging Applications 6 G0 l: n0 Y) p+ f# m7 G	Surface Technology Systems4 n6 z0 O. K. d x* B( ]

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