標題: 關於時序約束 [打印本頁] 作者: cosmosd 時間: 2009-11-3 09:49 AM 標題: 關於時序約束 各位，在綜合或者後端，輸入的input delay,output delay都是針對輸入輸出管腳，那麼對於模組或者系統內的中間信號呢？工具是自己根據庫工藝參數進行優化？那麼內部的優化有沒有裕量啊？由於工藝的偏差，又怎麼保證內部信號的時序對呢？作者: yytseng 時間: 2009-11-11 10:13 PM
跑 STA (static timing analysis) tool * K a) b3 G" m e- o) Z9 ^' A4 X% {* B) u/ M6 q
ex. synopsys primetime, or cadence timing system作者: lee100 時間: 2012-1-9 01:39 PM
STA only cover synchronous design. Designer has pay attention for asynchronous design make sure clock frequency and waveform same as function mode and all flops must constraint by its clock.