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標題: 7/29 Cadence Tech Forum 2010 [打印本頁]
作者: heavy91    時間: 2010-6-28 02:28 PM
標題: 7/29 Cadence Tech Forum 2010
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. j4 R5 U/ r! ^& |3 G8 d, fCadence益華電腦為電子設計產業提出設計的未來之路!  提供一個從設計開始到系統整合，適合於系統整合、應用開發與系統驗證的完整平台，這就是Cadence所勾勒出的EDA未來之路。EDA360願景能夠讓半導體公司建立威力強大的產品，讓消費性技術供應商能夠運用硬體、軟體與服務結合的生態系統，提供元件平台，能夠幫助公司具備更高競爭力與獲利力。   X2 V$ W: @' J
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　Cadence Tech Forum 2010讓所有電子產業設計專家能夠會見彼此，與Cadence益華電腦使用者、設計開發工程師， 和各業界專家一同討論，一同激勵電子設計產業的新願景。同時Cadence Tech Forum 2010亦提供了一個機會，了解 Cadence 益華電腦和其他友好夥伴共同開發的解決方案，與如何運用 Cadence益華電腦技術進行創新與研發。
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% g8 ?" X) G9 s5 W. p　今年Cadence Tech Forum 2010活動議題涵蓋廣泛，其中包括幾個最令人矚目的話題: 低功耗設計、先進製程下的設計實現、正規驗證、 constraint-driven設計、系統封裝設計和電子系統層級設計等。  O) N1 O( z* a# [, e* z9 b, U
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　歡迎參加Cadence Tech Forum 2010，讓你有機會更進一步了解Cadence益華電腦新的解決方法和產品特性，以及未來產品願景與策略。
作者: heavy91    時間: 2010-6-28 02:28 PM
TimeSpeech// J- c2 y" H1 V
Platform		TopicSpeaker
09:00~09:30Registration
09:30~09:40OpeningWelcome Remark

Veronica Watson,& R# r) v; p* T- e4 Y+ ~
AP President of Cadence Design System- z2 z4 A- O5 v' i
Willis Chang, 5 Q& P# t2 ], u6 }3 z( t- c/ ]% |
Country Manager of Cadence Taiwan
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09:40~10:10Keynote EDA 360: The Way Forward for Electronic Design

Charlie Huang,   n  E6 M& J, M
Senior Vice President and % ?* o9 o7 ^- P  t( g
Chief Strategy Officer

10:10~10:40
( q2 G. y% s2 h8 f! cKeynote		Cadence open integration platform with integration-optimized IPBrian Gardner,
8 ?4 O( c/ G$ J; [7 }- NGroup Marketing Director, New Business, Cadence
10:40~11:00Break (Proceed to Breakout Rooms)
Custom Design
0 [6 k$ y. T' P  u3 _8 d(Meeting room A&B, 13F)
11:00~11:50CD01TSMC AMS Reference Flow

M. J. Huang,
) t6 H+ j- Z( z% QTSMC

11:50~13:30Lunch
13:30~14:20CD02Virtuoso IC Design Platform 6.1.4 - Analog Design Exploration and OptimizationAlex Wang
14:20~15:10CD03Virtuoso What's New 6.1.4 - Virtuoso Advancing the Art of Custom Design Kevin Tsai
15:10~15:40Break
15:40~16:30CD04Advanced 32/28nm Node Challenges & Solutions - Enabling Fastest Time-to-VolumeEason Lin
Functional and System Verification
; F+ r% @; f6 F. |(Ballroom C, 10F)
11:00~11:50FV01Predictable System RealizationMichael McNamara
11:50~13:30Lunch
13:30~14:20FV02
2 M1 q! N0 O/ {6 [Cadence TLM Design & Verification with C-to-Silicon Compiler		Mark Warren
14:20~15:10FV03Cadence TLM to GDSII flowRich Owen
15:10~15:40Break
15:40~16:30FV04Cadence TLM Verification Cadence Expert
Digital Implementation
/ {7 X2 p0 b& k* R. `(Ballroom A, 10F)
11:00~11:50DI01Digital Implementation Update at TSMC Reference Flow 11 Cadence Expert
11:50~13:30Lunch
13:30~14:20DI02DoT/MSoT for Mixed Signal Demo Mladen Nizic
14:20~15:10DI03EDI System Roadmap: Encounter Digital Implementation System - Enabling "More than Moore"Wei Lii Tan
15:10~15:40Break
15:40~16:30DI04EDI System 9.1 UpdateCadence Expert
Logic Design # c' O& v; ?5 p
(Ballroom B, 10F)
11:00~11:50LD01Cadence Logic Design Product RoadmapYoon Kim
11:50~13:30Lunch
13:30~14:20LD02Phyical Predictability in RTL Compiler SynthesisMark Ou
14:20~15:10LD03Conformal ECO DesignerB. C. Shih
15:10~15:40Break
15:40~16:30LD04Can your spreadsheet do this ---- Innovative applications of pre-RTL chip planningAnis Uzzaman
System and IC Packaging ( z" l3 G2 P2 q! ]2 b6 F
(Meeting room C, 13F)
11:00~11:50SPB01SiP and 3DIC/TSV Design in TSMC Reference Flow 11.0
$ ~- m' a8 b  }Mike Peng, : J* J" Q5 X: p; |
TSMC
11:50~13:30Lunch
13:30~14:20SPB02What's New Update for 16.3 Allegro Package Design and SI Simulation?

Joseph Kao4 T% W3 a3 A( h
Thunder Lay

14:20~15:10SPB03Distributed Co-design for IC-Package-BoardThunder Lay
15:10~15:40Break
15:40~16:30SPB04Design issues from IC to package: Managing Package Outsourcing EngineeringKevin Liu
16:30~16:45Lucky Draw(Ballroom A, 10F)

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