標題: Circuit and Layout Co-Design for ESD Protection in BCD [打印本頁] 作者: semico_ljj 時間: 2010-7-3 10:06 AM 標題: Circuit and Layout Co-Design for ESD Protection in BCD Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process 2 l5 i9 n9 C' _1 v7 C g# O* f9 A4 V9 ~ z
Wen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE7 V6 y' `/ D* G
) U+ W1 W0 b( E8 V8 L" k* M
Abstract—The n-channel lateral double-diffused metal–oxide–( _. Y$ I% b- L- ~2 V( {
semiconductor (nLDMOS) devices in high-voltage (HV) technologies2 G( v# s3 `* S. f, S2 J
are known to have poor electrostatic discharge (ESD) 4 Z4 Y: L& Y0 W9 M: Vrobustness. To improve the ESD robustness of nLDMOS, a co-design 5 E- d6 o5 R& k+ [method combining a new waffle layout structure and a trigger ) y$ ~5 c1 U! Z( Q @3 h& D' `circuit is proposed to fulfill the body current injection technique* | ]& T8 A% W
in this work. The proposed layout and circuit co-design method / \$ L% K. W, Z* @9 Pon HV nLDMOS has successfully been verified in a 0.5- m 16-V- ^. L2 \. z3 N
bipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD9 m, t9 B' b8 h
process without using additional process modification. Experimental" N; r1 F( d6 {( e/ u) ^% L
results through transmission line pulse measurement1 {( S/ a3 Q9 o3 Q
and failure analyses have shown that the proposed body current 0 F7 \$ \9 ?8 s1 J5 u# n6 dinjection technique can significantly improve the ESD robustness6 w- f; y8 E& z1 R) @
of HV nLDMOS. # ~& C6 s+ n- C1 \* E) l% c( p5 m. b7 q7 m S2 g( s3 K+ V x) m
Index Terms—Bipolar-CMOS-DMOS (BCD) process, body 1 ^8 V; y' |/ V: D# Kcurrent injection, electrostatic discharge (ESD), lateral double-diffused 3 D2 {1 q$ m. R8 D+ m8 [# X: Umetal–oxide–semiconductor (LDMOS).作者: xp212125o 時間: 2010-7-28 01:46 PM
看起來有幫助2 K/ }4 E% U$ W0 Q9 ^) v5 B) O' U
感謝分享 4 {2 J& m5 C6 _( c- J, e# E! k先下載來看看4 I$ [# B9 e6 A& l% D' q" [3 W" _
thank you ~