Mentor Graphics（明導國際）誠摯邀請您參加設計驗證方案研討會，來自美國總公司的技術團隊將於現場與您分享目前最先進的設計驗證流程；同時，透過不同主題為您展示得以在SoC設計中提供高度效益的最新驗證技術。 & G. [4 ^0 M& A
設計出低功耗、高效能的晶片是每個工程師的目標與期許。為此，研討會的各個議程將對此分享明導國際在設計驗證模擬過程中的各種解決方案；希望透過這樣的技術資訊交流，為您找出改善關鍵、協助您修正驗證流程及提升驗證能力。
時間：2011/5/10（二）
地點：新竹國賓飯店11樓 竹萱廳（新竹市中華路二段188號）
Agenda:
| 08:30-09:00 | Registration |
| 09:00-09:50 | Keynote by Steve Bailey – Verification Trends » Abstract 6 {7 [+ z( J' q @# E R$ Y ( o. u- j7 C" c+ s, [. C Keynote by Steve Bailey – Verification Trends" Q+ w; S1 }1 S* b1 D The challenges of verification continue growing exponentially. Through advances in technology and methodology, verification productivity has improved dramatically over the past decade. Yet, the continuing growth in the size of verification teams and the amount of project time dedicated to verification indicate the need for greater advances in productivity. As we enter the era of SoCs, verification complexity will be driven by increased design complexity of multiple cores running many applications to deliver on-demand content in consumer devices such as tablets and smartphones.5 `7 x& f5 F% x: U It is clear that verification must be transformed in order to deliver the productivity that will enable the next generation of multi-core SoC consumer electronics. Innovative technologies that deliver 10-100x advances in verification are required. As the impact of software in electronic systems grows, verification solutions must expand to enable co-verification with advanced verification technology. Comprehensive solutions and methodology will integrate these innovative tools and enable real-time progress tracking, trend analysis and increased automation and efficiency of the verification process. If you need to transform your verification processes to dramatically boost productivity, radically decrease time-to-coverage, and more effectively and efficiently manage your verification processes, then the Transforming Verification seminar is for you! Close7 Y1 \* j, h9 O! E6 R |
| 10:00-10:50 | Verification Management and Planning » Abstract 3 [/ v) p g- P , \ w# x1 f* J, |4 N Verification Management and Planning When verification is not under control, project schedules slip, quality is jeopardized and the risk of re-spins soars. What’s required is a common platform and environment that provides all parties – system architects, software engineers, designers and verification specialists – with real-time visibility into the project. And it’s not just to the verification plan, but also to the specifications and the design, both of which change over time. There are three dimensions to any IC design project: the process, the tools and the data. Mentor Graphics Questa® Verification Management offers a comprehensive approach to verification management that handles them all. With the flexibility which allows enabling technologies to be deployed either alongside current legacy verification environments, incrementally replace them in a modular fashion or benefit from the power and integration of the complete solution., O) \' ]) q& A5 C* \0 T Verification management should be based around a structured process but also requires the tools to allow this process to be automated. Given the rise in design complexity, it’s no surprise that data management is increasingly the foundation of any verification management activities. This session will cover:2 g' [2 g5 v7 K+ j( \* p
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| 10:50-11:10 | Break |
| 11:10-12:00 | Accelerating Coverage Closure » Abstract 6 @2 B% e- }. P$ Q6 O6 `2 @1 w) | Accelerating Coverage Closure Achieving functional coverage closure in today’s complex designs is challenging and time consuming. It is common for a verification team to spend a disproportionate amount of time attempting to achieve the last 20% of functional coverage, by identifying corner cases manually, struggling to create overly complex constraints, and often times resorting to writing lengthy directed tests to target these cases. Mentor Graphics has a proven methodology to accelerate functional coverage closure, freeing up resources to achieve more verification. Questa’s Intelligent Testbench Automation solution generates stimulus according to the user’s functional coverage goals, eliminating redundant stimulus and efficiently targeting corner cases. The result is 10x to 100x faster functional coverage closure. This session will discuss5 Y! G; Q' ]0 L" z N& O1 F+ x
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| 12:00-13:30 | Lunch |
| 13:30-14:20 | Active Power Management Verification » Abstract & f& J5 G) t9 T$ z* S6 o% u [ 5 B2 V% k6 W% k Active Power Management Verification Power management has become a critical aspect of electronic systems design. Driven by customer demand for more functionality and longer battery life in portable electronics, and enabled by advances in process technology, minimizing power consumption is now mandatory. This session presents Power Aware Simulation and describes how it is being used today to verify active power management in complex SoC designs. The presentation will explain how IEEE Std 1801 UPF is used to define the power management architecture for a device and how Power Aware simulation enables visualization and debugging of active power management and its effect on design functionality.9 W7 _, C6 R6 P. m r# v Close |
| 14:20-15:10 | Formal AutoCheck - The Push Button Way to Find Bugs » Abstract ; M" L/ ]4 Q2 O+ I : N/ m2 e; f: u s# ] Questa AutoCheck - The Push Button Way to Find Bugs+ b6 r8 n4 u2 p& f& M# t The Mentor Graphics Questa Automatic Design Checks allow any designer or verification engineer to quickly verify their design for common functional design issues. This technology makes use of automatic assertion creation techniques and formal verification sequential analysis to allow verification to take place before a testbench is in place or anyone has written an assertion. Common design checks this tool provides range from FSM checks, deadcode/stuck checks, arithmetic checks, register and bus checks to name a few. Also included is a series of checks for X verification and initialization effects in your design. The user also has the ability to automatically generate an exclusion file for improving simulation code coverage thus reducing the amount of time wasted trying to hit unreachable states.. `; Z* w4 {. ~% N5 l Close+ t1 Y5 @& ?0 @8 O4 k 4 H& X6 z; T2 ~9 J) b) U& T# v0 _ |
| 15:10-15:20 | Break |
| 15:20-16:10 | Industrial-Strength Clock Domain Crossing Verification» Abstract / h' {! Z2 M" G i7 X6 S: K7 L Industrial-Strength Clock Domain Crossing Verification More than 90% of today’s designs contain multiple clocks, and all such designs can potentially fail if communication between clock domains is not correctly synchronized. This session presents CDC Verification and describes how it is used in world-class production verification flows to detect and eliminate potential problems in multi-clock designs. Questa CDC Verification automatically identifies clock domains, recognizes and classifies synchronizers, generates synchronization protocol assertions, and attempts to verify those assertions statically. Also automatically includes protocol assertions in simulation for dynamic CDC verification, and it includes metastability models that reflect the timing uncertainties introduced by synchronizers to ensure that any reconvergent CDC paths behave correctly.6 e3 d) h n. S& u; s2 o Close 7 o o. M& |9 t, G" _6 B |
本次研討會全程免費，因場次席位有限，敬請盡早報名。( ~& p( h+ I, V6 ^8 h$ J3 d3 |3 j
活動相關細節，請電洽明導國際 陳小姐 電話：02-87252000