標題: 6/5-9 San Diego "Design Automation Conference (DAC)" [打印本頁] 作者: tk02376 時間: 2011-5-24 04:44 PM 標題: 6/5-9 San Diego "Design Automation Conference (DAC)" - h' H/ `/ \; w4 f8 m% |
The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. Now in its 48th year, DAC features a wide array of technical presentations, as well as more than 200 of the leading electronics design suppliers in a colorful, well-attended trade show that, literally, attracts stakeholders from around the world.* e0 j& C* f* r" R. p8 K
4 s# s5 N" p3 H5 ~Some of the highlights of this year's DAC include: + b9 }1 U: m! q2 g - c4 C% S5 w1 v$ v! ^9 L
Keynotes by industry leaders/visionaries
Technical Program (panels, special sessions, User Track)
Forums, tutorials, and workshops
Management Day
IC Design Partner pavilions and sessions
Hundreds of exhibit booths
Adjunct events
Colocated events
Awards for professionals and students
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And there's much more.' g; R, a( U4 ]* S
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Join us in San Diego, June 5-9. Registration is open!作者: globe0968 時間: 2011-6-14 11:49 AM 標題: GSA Releases 3D IC Design Tools & Services Tour Guide at DAC 本帖最後由 globe0968 於 2011-6-14 11:50 AM 編輯 $ Z5 P, Y7 ~& Y% |
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On June 6, GSA's EDA Interest Group and 3D IC Working Group Chairman Herb Reiter moderated a panel at DAC entitled "3D IC: Myth or Miracle" - a somewhat skeptical title. Herb and other leading industry executives addressed the challenges of 3D IC design and manufacturing and what is needed to make this a mainstream technology. 2 W5 J( |3 u9 c
* X2 u, l1 a" X0 ~ d1 KThe panel began with each panelist showcasing how they are currently using 3D or the interposer-based 2 1/2 D technology. As expected, most are currently using 2 1/2 D as it is a way to go through the cycles of learning with little risk to the company. Suk Lee of TSMC helped to make 3D IC less of a myth by presenting a prototype of a 3D IC wafer manufactured by the company. Ivo Bolsens, CTO of Xilinx, brought a sample of their 2 1/2 D solution and passed it around the audience of approximately 250 people. Riko Radojcic from Qualcomm outlined what they learned about 3D in their cooperation with partners and suppliers during the last four years. % k* z% H; j& B" |8 P; v3 v/ U+ `, f9 H
Members of the audience voiced that there are challenges associated with the evolutionary technology such as power; however, the panelists emphasized that many of the issues associated with 3D IC are not specific to the technology, but also happen today with 2D SoCs. They are certain that 3D IC will be a major driver; however, a solid roadmap, a strong ecosystem as well as design and manufacturing standards must be agreed upon to make 3D and 2 1/2 D cost-effective solutions for many applications. The question remains: Who will establish these and what technology and business knowledge as well as skills must they possess? 2 P1 g( {* X( M- I( B/ e: a # ]6 U% x( n4 T1 d, k1 C) F3 VMr. Reiter closed the panel by expressing his plan to present at next year's DAC a number of application examples to show the versatility, cost-effectiveness and other user benefits of 2 1/2 D and 3D technology. Then he introduced and distributed the 2nd edition of the 3D IC Design Tools and Services Tour Guide created by GSA's 3D IC Working Group. The Tour Guide is a compilation of inputs from EDA, R&D, market research and services companies that have committed significant resources to developing 3D and 2 1/2 D technology to accelerate market acceptance of this important paradigm shift. Readers of the Tour Guide are able to view the 3D IC capabilities of these companies. 9 ~9 T# r1 G, A! ^; l* y ( {* z2 \* T5 \ v1 T, ODownload the Tour Guide8 E. m- s- T' A# K5 v4 D3 q- ^
The Tour Guide is complimentary to the industry and available for download by clicking here.
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