2 Z# I" U- k) Q消費性電子產品佈局設計 主要工作內容：個人行動通訊、數位 廣播電視、無線區無 線 區 域 網 路 WLANs(如IEEE 802.11a 、藍芽等 )？2 R7 [; Z0 R: l2 M3 x6 v
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通常工作中，哪三項問題最多？最需經驗交流？作者: ranica 時間: 2012-2-3 04:56 PM
招聘公司：A famous IC company" z5 v- b$ K9 V: B7 I
招聘岗位：Analog layout designer8 j' J" i# t5 m& J
工作地点：Shanghai 5 }1 p( S' ~3 ?- J% b 6 L" \1 b. m3 o/ o+ m5 W& s岗位描述：9 B6 v& j$ _! j! X4 j
Job Function 1: Design block analog circuit. 2: Design block and top-level analog layout. 3: Build analog and digital pad library. ! r1 ?8 r) {9 A/ O1 B1 n
$ g/ k0 o; F1 p- [, L4 l职位要求：2 \; `/ i/ Y' n
Skills/Experience 1: Familiar with Composer, Virtuoso, layout XL, Calibre physical verification. 2: Solid fundamental knowledge in circuit, semiconductor and layout, such as matching, floor plan, size estimation. 3: Experience in high speed SERDES design and layout. 4: More than three years of analog circuit and layout experience. Responsibilities Education Requirements Bachelor degree in Semiconductor, Electronics Engineering.作者: ranica 時間: 2012-2-3 04:56 PM
招聘公司：a start-up company with high performance bletooth and Wifi technology" c. d- f) D; c' d" ~0 K
招聘岗位：IC Layout Engineer : W4 T# W z" L1 Z工作地点：Shanghai $ R, `9 ?( F( J0 v7 `6 b* i$ G, m6 n
岗位描述：( X ~& c$ c7 W" x& N% g
Job description The candidate will be responsible for RF and analog block circuit layout and verification including DRC, LVS, and antenna rule check etc, chip level floor planning and layout integration. Responsibilities - RF and analog block circuit floor planning and physical layout - Layout verification including DRC, LVS, and antenna rule check etc. - Chip level floor planning and layout integration - ESD pad layout : e+ G& O/ l- ^5 S8 Q1 d" S * q/ a5 u/ D( h m; K职位要求： f; u8 o4 B- U; X I2 @5 U: C/ o( T
Qualifications - BS or above, Electrical Engineering - 2 year's or more industry experience is must - Successful tape-out experience is must - Knowledge about bulk CMOS process - Familiar with Layout and verification tools including Cadence virtuoso, and calibre LVS/DRC/PEX, etc - Good team work with circuit designer and backend designer is must. - Can read/write Calibre rule file is preferred.作者: ranica 時間: 2013-5-17 02:42 PM
资深 IC layout工程师1 t' q: q6 P; R( p% {
客户 A global PC leading enterprise" f: v& n8 X4 a* _- d
地点 Shenzhen6 V- B1 ~$ v d