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標題: 6/9,16 Key Enabling Technologies for 3D IC/Si Integrations [打印本頁]

作者: mister_liu 時間: 2012-5-11 10:05 AM
標題: 6/9,16 Key Enabling Technologies for 3D IC/Si Integrations

101年通訊與電腦整合應用人才培訓計畫

=科管局補助2/3學費=

特聘 ITRI Fellow 劉漢誠博士，歡迎報名

作者: mister_liu 時間: 2012-5-11 10:06 AM

課號	RF4307
課名	Key Enabling Technologies for 3D IC / Si Integrations
授課教師	劉漢誠 John H. Lau ( ITRI Fellow of ITRI since 2010... ) * b2 D- z0 c" V7 V 劉博士目前受聘於工業技術研究院，他已經在電子、光電和汽車產業，從事研發、製造的工作超過30年了，編寫或是合著的評論性技術文章超過250篇，撰寫的書籍超過100多個章節，同時舉行或受邀參加過230場專題研討會和演講，自1986年起，在IEEE、ASME、IPC、SMTA、ASM、NEPCON以及APEX教授電子、光電封裝等課程，深獲許多知名企業的工程師與經理人好評。 John Lau博士簡歷如下: ITRI Fellow of Industrial Technology Research Institute since January 2010. The visiting professor at Hong Kong University Science & Technology for one year. The Director of Microsystems, Modules & Components(MMC) Laboratory with Institute of Microelectronics in Singapore for 2 years. The senior Scientist/MTS at HP/Agilent in US for more than 25 years. ASME Fellow. IEEE Fellow since 1994.
課程大綱	The key enabling technologies for 3D IC integration are, e.g., electrical, thermal, and mechanical designs and tests, known good die (KGD), TSV (through silicon via) forming and filling, wafer thinning and handling, thin chip strength measurement and improving, lead-free microbump forming and assembly, low temperature C2W and W2W bonding, and thermal management. In this course, all these enabling technologies (except electrical) will be discussed. $ H7 E* w6 C5 U% T Moore's law has been the most powerful driver for the development of the microelectronic industry. This law emphasizes on lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC). On the other hand, the integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC/Si integration, which is a very complicate subject. It involves component and system designs, FAB, packaging assembly and testing, material suppliers, and equipment suppliers. The key enabling technologies for 3D IC integration are, e.g., electrical, thermal, and mechanical designs and tests, known good die (KGD), TSV (through silicon via) forming and filling, wafer thinning and handling, thin chip strength measurement and improving, lead-free microbump forming and assembly, low temperature C2W and W2W bonding, and thermal management. In this course, all these enabling technologies (except electrical) will be discussed. Most of the materials are based on the technical papers published within the past 3 years by others and the instructor.% y( s4 g' e' g+ N0 V3 H4 L After completing this course, you will be able to: •Understand the state-of-the-art and trends of 3D packaging, 3D IC integration, and 3D Si integration & Z* B9 C3 x! v6 }) I: M5 q% p•Understand the key difference between 3D packaging and 3D IC integration+ l h" \. T& ^7 o& w4 s •Understand the key difference between 3D IC integration and 3D Si integration 4 [; O0 O* }4 v" {" H8 [4 d& x$ f. L •Know RoHS compliant (green) electronics products* A. J, o8 X' {, ~4 F •Understand all important aspects of flip chip technologies 4 S4 h3 z! T6 u: S7 O•Understand all important aspects of wafer level packaging; H1 \|# j6 i* R8 Y v •Understand all important aspects of 3D IC integration and WLP 2 P/ v2 \. m* {' ]& G$ D: H1 ?•Understand the impact of TSV on 3D IC Integration and WLP 0 G4 m9 c" e* ^8 i, \' \|•Understand the 5 key process steps of TSV1 P+ C9 u8 Y1 ^ •Know the impacts of TSV interposers on thermal performance of SiP5 \' `7 Y0 i# J7 L; \| •Know the impacts of TSV interposers on Mechanical performance of SiP ( G9 {5 p, N- v% l•Know how to fabricate and characterize TSV interposers/chips* Q7 H( [1 t# ?. y# [, r •Know how to fabricate and characterize 3D chip stacking% Y+ V/ J6 j* B: j/ l' B$ ^# `9 w •Know how to fabricate and characterize lead-free solder microbumps ( A; f+ T* b. V0 ~* y% r7 l% o•Know how to assemble and reliability assessment of lead-free solder microbumps" b8 f/ N0 I7 K; i0 u4 E9 \7 n •Know how to design and perform in-situ stress measurements % U4 {( F3 I& ~: X. Q7 g•Know how to do wafer thinning and thin-wafer handling) x5 ^0 z- Q6 X& X* s& K- P! o •Know how to do lead-free low-temperature C2C, C2W, and W2W bonding 2 s8 i! F9 W! I•Know how to do CMOS image sensor with TSV O+ b& A4 O; l0 T$ f$ J4 {•Know how to do 3D MEMS and IC integration 6 ]. P& U. {8 R•Know how to do 3D LED and IC integration6 y' L7 P) `. u •Know how to do thermal management of 3D IC stacking2 \|' S- ?0 L3 o7 v •Integrating 3D IC integration and WLP into your SMT assembly) _4 I; r" M, ?8 N ~, G •Know the critical issues of 3D IC integration 0 M, ^% u4 P: h; l3 b•Know optoelectronic0 N$ j' z1 A6 ]8 L& H# g+ x •Know optical PCB
建議背景	If you (students, engineers, and managers) are involved with any aspect of the electronics industry, you should attend this course. It is equally suited for R&D personals and scientists.
授課時間	9：00～13：00 14：00～19：00(附餐)
授課地點	交大工程四館824教室
課程費用	優惠價4500元
報名截止日	2012-06-08 # s8 ?6 K+ ?, c2 X E/ ^截止
授課日期	6/9,6/16(Sat)

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