標題: 8/27(一) 台大 Design Consideration for ESD and Latch-up [打印本頁] 作者: tk02561 時間: 2012-8-17 03:11 PM 標題: 8/27(一) 台大 Design Consideration for ESD and Latch-up 時間：101年8月27日（一）下午2:00-3:00: i% b0 g7 L0 S9 g# S" m% G, q
地點：國立台灣大學電機二館124會議室 9 n7 r) v$ ]0 ~演講資訊如下： ; ~. m6 s' e9 i7 y1 P% ? % c4 r: a. q; x+ v0 G. V& D1 _講題esign Consideration for ESD and Latch-up - R8 Y9 z C7 b! E5 Q6 u- X # L! t+ J7 s; j8 F大綱: " S. o A r9 G# ^; H: TDesign Consideration for ESD and Latch-up ESD and latch-up are two of the most frequent reliability issues for commercial IC's. They contribute more than 25% of total IC failure during manufacturing and in the field. While often overlooked in the design process, as other factors such as performance and cost always attract most of the attention, design for reliability eliminates major hurdle in product introduction. The presentation describes typical reliability requirement, testing, and qualification for commercial IC's and the ever-increasing challenge posed by advanced CMOS technology. Various approaches that are commonly adopted by industry to ensure ESD robustness and latch-up immunity will be discussed. The emphasis will be mainly for custom analog and RF IC application. . W+ ^/ M3 {# |! n
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講者簡歷: & i( d7 N8 }5 I$ v9 S* ?Tzung-Yin Lee joined Skyworks in March 2003, where he is presently the senior manager in charge of Foundry Technology Modeling, ESD, and Device Characterization group. From 2001 to 2003 he was with Maxim Integrated Products working on WLAN product development. From 1997 to 2001, he was with Conexant Systems, formerly Rockwell Semiconductor Systems, working on the development of the RF front-end device for Bluetooth and coreless application. He received the B.S. degree from National Chiao Tung University, Hsin-Chu, Taiwan, in 1991, and the M.E. and Ph.D degrees from University of Florida, Gainesville, Florida, in 1992 and 1997, respectively. He has authored and coauthored more than two dozens of research papers in high-speed and high-frequency device modeling for RFIC design application.# m* k) W! U$ F8 H( u
esign Consideration for ESD and Latch-up