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Synopsys Accelerating AMS Design and Verification Seminar | 時 間 : 民國102年6月27日 星期四 (09:00am ~ 04:00pm). c3 c. w! K( i
地 點 : 新竹國賓飯店10樓 ( Ballroom A / 新竹市中華路二段188號)+ D4 O! m4 ?& n
- _7 H9 O$ D2 t! n I新思科技 (Synopsys) 將於6月27日假新竹國賓飯店舉辦 AMS Design and Verification Seminar,這項研討會是去年合併思源科技後,首次結合雙方類比混合訊號解決方案的大型活動,將介紹當前最先進的技術,強化對台灣地區客戶的服務,竭誠邀請舊雨新知熱情參與。8 {7 i8 \; m) H% Q
此研討會將特別邀請Synopsys總裁暨共同執行長陳志寬博士(Dr. Chi-Foon Chan)致辭、Synopsys類比混合訊號事業群(AMSG)副總裁李炯霆博士(Dr. JT Li)擔任Keynote,以及聯發科技Corporate VP Dr. Lawrence Loh (陸國宏博士)擔任Customer Keynote,讓與會貴賓能凝聽並汲取當前AMS Design的各種新知。而為了鼓勵參與,我們也特別準備iPad mini、ASUS fonepad、數位相機等抽獎獎品,前100名報到者並有早鳥禮物 (實用多功能工具組),歡迎共襄盛舉。% _+ \& T, `4 _6 Q' Q, b
- W; W C7 W. ~; s: z: t$ iOverview
$ ]: T0 t; P8 ?Attend a FREE Synopsys seminar to learn about the latest developments in AMS and custom solution from Synopsys and learn how to utilize these new capabilities effectively to increase AMS simulation throughput, achieve higher level of mixed-signal verification and custom implementation productivity. We will cover advancements in SPICE and FastSPICE circuit simulation, mixed-signal verification, AMS debug and analysis, characterization and custom layout implementation. 8 b8 n0 q F S8 Q1 v
Who Should Attend
* E$ D, l: ~- vCircuit designer, layout engineer and manager who want to learn how Synopsys can improve custom circuit design, layout and verification productivity.
/ w/ Z, \/ x: W# Q, ^' L: P報名方法 : 請於6月24日前填妥附件報名表, 回覆至: AMS_seminar_TW@synopsys.com . k; h! p: u! U" E- F
贈獎辦法 : 凡詳細填妥問卷即致贈精美禮品乙份,並有機會摸中大獎! 3 ]6 r( Q" q+ \8 L
活動完全免費,座位有限,請即刻報名!(若報名額滿或現場報名來賓, 恕不保證座位!)! ~1 ^. H$ F0 p$ Z
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