標題: indicate the top challenges in your team’s verification flow [打印本頁] 作者: ranica 時間: 2013-9-3 03:35 PM 標題: indicate the top challenges in your team’s verification flow Please Check up to three... others (please specify): ... or you don’t know? # n2 d" q9 x0 H1 e6 W0 r& y# u
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Simulation compile performance ( l5 `' e. N O' ] VVIP quality 9 c* @7 Z) T! [9 B5 H
Coverage closure* ^3 A0 j# o0 r, m
Emulation 7 U: s9 J! b8 l) T0 FConstraint random verification (using SystemVerilog) # U6 ^' w+ g. N* E/ J! O% u/ r0 y" A
Regression management作者: mister_liu 時間: 2013-11-1 02:20 PM
Staff Hardware Based Design and Verification Engineering Lead ; N) ^/ g- N2 H0 D* f- ^( x1 A! O9 J" L) B Z- s
公 司：One world top EDA company 9 v, f+ _1 k+ X* H( [ y! m0 E工作地点：上海1 O+ [' s7 Q5 w5 `4 i# S, o5 S9 _ q
4 a) E: c7 n2 p1 U3 v* O9 oPosition Description: % Y. g8 T/ [3 K2 r
1. The Staff Hardware Verification Engineering Lead will be in charge of a team of field engineers to support advanced hardware based verification flow integration engagements with Cadence customers and provide easy-to-adopt packages and workshops to xx field application engineers and customers alike. f+ \3 ~ Y. v e& e
' Y" W. m m% l( Q- K2. He/she will focus on the technical aspects of the following hardware verification solutions for customer engagements as well as creating demos/workshops to train field AE and customers: 4 M3 @, T- [1 P9 A/ ~(1) xx Palladium HW Acceleration Platforms 3 R5 ^1 c' N" U, \* o5 @1 o0 f. c
(2) xx Acceleratable Verification IP portfolio ' l8 b0 n2 R: Z2 Y9 G# Y(3) CVA product integration with other xx products such as Incisive Simulation and RTL Compiler for power analysis7 a! s. a6 g8 x: m1 P
(4) HW/SW Co-verification solutions for SoC designs作者: mister_liu 時間: 2013-11-1 02:20 PM
Position Requirements: % P' V1 T6 e& U* }1 M' a, a
1. Experience: 6 d9 U: x5 p/ U
- Minimum experience required: 10 years 1 w3 W" ~+ P4 a% Q
- Expertise in RTL top-down design and verification methodology automation are required. This includes full hands on knowledge of writing and debugging Verilog, VHDL and SystemVerilog based D&V environments.' o( A& t5 Q1 F0 F4 I5 R* i5 B3 o3 d
- We would also like the candidate to have good knowledge of SoC design principles, embedded software development and HW/SW codesign and coverification. + ?9 u/ z* ?4 f& j [6 F9 t- Knowledge of UNIX, C/C++, other scripting programming languages ( Perl, TCL…) is highly desired # r8 L5 ?' K0 U8 [% z
- Strong verbal and written communication skills in English are required % k, N, |4 [. t- HW acceleration or In-Circuit Emulation or FPGA prototyping experience is a must + T) ^8 ^2 C1 H% m" T3 Y2 \- Hardware verification, including knowledge of HDL simulators and debugging simulations : x1 E4 y6 D( c& \6 [5 L/ }. a- Hands on experience with using design and verification languages like SystemC, SystemVerilog (IEEE 1800) and VHDL is a must. 1 C- q* l q& d- ^) x+ M" J/ o- Knowledge of embedded systems and software development for SoCs is a plus * i3 B5 A) G* \6 @; O! u' z$ |2. Education: / G0 S2 d; ?% c4 {2 O/ yIdeally the person should possess the BS/BE level of understanding of CS or EE Engineering concepts ' `0 t* l" x4 G8 R% }$ V! x- Minimum Education Required: education level of BS with 10+ years experience (or MS with 7+ or more years experience). 9 Q- w) ]2 S: u9 V, Y
3. Travel of 30% of the time should be expected.作者: tk02561 時間: 2013-11-19 08:58 AM
ASIC Digital Verification Engineer ! l' R) O4 F# s8 c公 司：A mobile chipset semiconductor company : t) o# P" O, v, z工作地点：上海 + ], \; _/ N6 y3 k : @ n, M( u) @3 w9 GResponsibilities: # b& N4 x' U+ t' O Make verification plan for one module or whole chip. 1 u. S9 x0 k0 i; D Build up and maintain module-level and chip-level verification environment 9 ^+ p$ x L' k! a E9 M* u) N8 ]: D
Verify ASIC digital design based on case list, and output verification report. - e( `* b0 Z' C) K H0 } Also responsible for lint checking and formal verification. 4 u3 o) }& M6 w6 B& P0 m2 ]
- d( j7 q2 p! E T1 \Qualifications: 3 h, v) _# c7 r# j1 y Proficiency in logic verification. $ j- _4 R! W% I3 H
Experience with Verilog logic design language. 0 r# v' ?7 T6 b9 O
Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language. % Y$ {9 V i. @1 _ Experience with UNIX/Linux simulation tools such as IUS or VCS. I! F3 `) _0 d" I% } Experience with C and C++ is a plus. 6 t- q" H& o* a Experience with C_SHELL, TCL or PERL is a plus. 4 S; x- V: z! Z+ c J! B1 N
Experience with UVM, OVM or VMM is a plus. 6 g, i# @. T/ ?& q, X
Good knowledge of SOC design is a plus. - Z- ~7 A3 x. X1 X) `7 F% z" M" c
Good knowledge of software design is a plus. % D% s, s8 K* e* h
Self-motivated and good team player. 5 b; c. w) A. \0 R/ g( @9 ^ MSEE or BSEE with 2+ years.作者: ranica 時間: 2013-11-26 09:29 AM
Staff Hardware Based Design and Verification Engineering Lead5 \$ k# c+ M$ A. u' M! w u
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公 司：One world top EDA company 5 {% N- ^/ R5 T工作地点：上海, M, P7 L7 j/ [! p9 I2 i
" P4 h' F+ {) p% c+ R% T7 \
Position Description: / x, Y b3 k; R) K& g& s: Q$ N1. The Staff Hardware Verification Engineering Lead will be in charge of a team of field engineers to support advanced hardware based verification flow integration engagements with Cadence customers and provide easy-to-adopt packages and workshops to xx field application engineers and customers alike. 1 d. Z v2 O/ q \* G ~0 u$ k6 \. s k+ M) _# p o2 ]2. He/she will focus on the technical aspects of the following hardware verification solutions for customer engagements as well as creating demos/workshops to train field AE and customers: $ M6 N/ U+ y, P4 o3 h/ O q
(1) xx Palladium HW Acceleration Platforms $ K+ k% P2 u6 Q! d" ?(2) xx Acceleratable Verification IP portfolio ! E V3 F @5 [; b6 i# h2 [1 W; ]$ Y" K
(3) CVA product integration with other xx products such as Incisive Simulation and RTL Compiler for power analysis* a1 m1 W, \8 N/ V
(4) HW/SW Co-verification solutions for SoC designs 9 b! U$ a5 f5 Q1 x' \" v/ e$ d# }, H, P. y2 r8 g3 L
Position Requirements: : z- \, p) c) {" y3 {' b0 Z) ]1. Experience: ( w3 F' g' L, z5 n# p% i$ E- Minimum experience required: 10 years 4 V. Q1 e5 }* [4 L2 _
- Expertise in RTL top-down design and verification methodology automation are required. This includes full hands on knowledge of writing and debugging Verilog, VHDL and SystemVerilog based D&V environments." K# | v5 d' t F+ {& x
- We would also like the candidate to have good knowledge of SoC design principles, embedded software development and HW/SW codesign and coverification.* |' v# T3 l* H; S
- Knowledge of UNIX, C/C++, other scripting programming languages ( Perl, TCL…) is highly desired 9 x9 Z3 J) y( O4 ?4 g" Y0 ]( A- Strong verbal and written communication skills in English are required ' w5 j: P# ?+ @! _4 ]- h2 o
- HW acceleration or In-Circuit Emulation or FPGA prototyping experience is a must - U7 o9 o; e& d8 I( {% ]- Hardware verification, including knowledge of HDL simulators and debugging simulations # r& | M" X; z
- Hands on experience with using design and verification languages like SystemC, SystemVerilog (IEEE 1800) and VHDL is a must. 2 h& \& }& ]2 f D7 S- Knowledge of embedded systems and software development for SoCs is a plus ! k) T, }& Z4 K: i& o2. Education: & F+ s9 V& j* ]& I1 b! ]
Ideally the person should possess the BS/BE level of understanding of CS or EE Engineering concepts - x! N- Q5 h* {; K
- Minimum Education Required: education level of BS with 10+ years experience (or MS with 7+ or more years experience). 5 i! @. A, T/ ?3 J8 [/ r3. Travel of 30% of the time should be expected.作者: ranica 時間: 2013-11-26 09:30 AM
Lead Physical Design Engineer（Shanghai）& o0 [: M+ Q) s/ R
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公 司：One world top EDA company ( |7 T* F; k( w& S& ]5 B/ E0 K工作地点：上海 $ K- W% s6 A" c) w6 O% ~, |6 R/ b: d
职位描述5 D% `) `" L9 g3 x4 E/ _6 X
-Perform physical design implementation, including synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design project management. x: [, [9 ?: }5 j) j-The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation physical design, methodology and flow development.$ l4 ]! U6 ? Y, p2 u0 e
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职位要求 / d& C) x2 {0 [0 U3 l: E# g! c& w9 z% ?1. BS degree with 10+ years of applicable experience, MS degree with 7+ years of applicable experience in electrical engineering, microelectronics. 0 x C. U7 k* H4 T, o, i
2. Experienced with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues. 1 O0 Z5 s9 t5 E- {+ g3. Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM. ! l7 n, a ~* ^. i
4. Successful track records of taping out complex, 65/40/28 nm SOC chips. & O u9 T' n& C9 T- o9 r7 V$ X
5. Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl. . N( X) Z9 o' v1 R/ {6. Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English