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標題: Which verification elements does your team use on your current design project? [打印本頁]
作者: ranica    時間: 2013-9-3 03:37 PM
標題: Which verification elements does your team use on your current design project?
Pls check all that apply, unless you don’t know?
作者: ritaliu0604    時間: 2013-10-22 03:35 PM
Staff Hardware Based Design and Verification Engineering Lead
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公      司：One world top EDA company- g1 |0 T/ x# P- P+ d
工作地点：上海
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  d4 ~/ h# A$ cPosition Description:  
1 b* Z% D! H, q5 q9 I& H+ h1. The Staff Hardware Verification Engineering Lead will be in charge of a team of field engineers to support advanced hardware based verification flow integration engagements with Cadence customers and provide easy-to-adopt packages and workshops to xx  field application engineers and customers alike. + p# Z4 j9 H" O
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2. He/she will focus on the technical aspects of the following hardware verification solutions for customer engagements as well as creating demos/workshops to train field AE and customers:
, M) a6 X1 A, u8 G. B6 F/ v(1) xx  Palladium HW Acceleration Platforms
& c+ j) p- j! Y(2) xx Acceleratable Verification IP portfolio
7 a! z3 m: n& p1 `; l(3) CVA product integration with other xx products such as Incisive Simulation and RTL Compiler for power analysis' d% I# H) y3 H' R
(4) HW/SW Co-verification solutions for SoC designs
作者: ritaliu0604    時間: 2013-10-22 03:35 PM
Position Requirements:  9 P$ `; X9 o& w8 n! E" u  @
1. Experience:  7 F! m$ M- v6 V3 \) R! z: C
- Minimum experience required: 10 years  , @  W' L/ L- N/ @3 r
- Expertise in RTL top-down design and verification methodology automation are required. This includes full hands on knowledge of writing and debugging Verilog, VHDL and SystemVerilog based D&V environments.
( U4 h6 v) s5 i7 o, j" h- We would also like the candidate to have good knowledge of SoC design principles, embedded software development and HW/SW codesign and coverification.
' d" x) _1 p% z  i/ Q+ r+ I- Knowledge of UNIX, C/C++, other scripting programming languages ( Perl, TCL…) is highly desired
, ^5 x7 B& h: _8 j, L* u- Strong verbal and written communication skills in English are required  
- ?" A( R3 o* n. c- HW acceleration or In-Circuit Emulation or FPGA prototyping experience is a must
, X9 f' f4 ^6 E( r; x' J' C4 m. e- Hardware verification, including knowledge of HDL simulators and debugging simulations , G0 V) s5 e0 B! s
- Hands on experience with using design and verification languages like SystemC, SystemVerilog (IEEE 1800) and VHDL is a must.
1 f: S5 E* b/ \9 U, r* e$ B  Z5 }- Knowledge of embedded systems and software development for SoCs is a plus
) D/ ?& |4 x! E# }& q3 C2. Education:  2 g5 G! h$ z2 [1 v! j
Ideally the person should possess the BS/BE level of understanding of CS or EE Engineering concepts  
  ]1 N6 ~9 E9 s; h- Minimum Education Required: education level of BS with 10+ years experience (or MS with 7+ or more years experience). 9 i( z* [: W: B9 [6 {5 \
3. Travel of 30% of the time should be expected.
作者: ranica    時間: 2013-12-12 09:14 AM
Senior Physical Design Engineer
; v6 Z* o/ D1 K公      司：A famous IC company
5 ]7 c6 G8 J: d/ Y9 {* g* ^8 W" F工作地点：南京3 h( w( Y0 Z* Y, M4 a

  z- X6 Q) _6 o8 H$ tKey Responsibilities  . ]. |% f: B) r$ K# N
Depending on experience, key responsibilities will involve some of the following:  ; A6 w. u$ l" @  [) W. w/ ]
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
2 J1 L$ B) z& ~* xAs a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
3 P$ \' N$ ~: D  l& GLeading a team of physical design engineers and resolving the technical related issues.  
4 ^  v7 G2 o& W# }3 d4 iCrosstalk analysis, power analysis, and static timing analysis.  
8 U4 ]6 _8 V8 L6 `Write scripts in Tcl to improve productivity.  % [2 B% F/ G' ^7 z* P- v
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职位要求
) @$ }; H* Q6 a& VExperience: 5+ years in physical implementation engineering    7 X) U- U4 t  _' P' b
Essential skills  * Y; E) f8 r' x: a8 o1 X
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills  $ t  I: E0 ^: Y0 v, @$ _$ E' q
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation.  
$ H1 D, g# v6 G7 v3 m8 YGood programming skill. Capable of writing Tcl or Perl.  
5 I$ {; b( {) q; VFamiliar with synthesis, static timing analysis.  
2 @/ P8 v3 D4 cSelf-motivated team worker, good verbal and written communication skills in English.  4 V; d) ~3 G2 }
Technical and team leadership proffered. Previous management experience highly desired.  + h- o" G. @$ f( P  ?5 W
Experience with synthesis, DFT, and verification is preferred.
作者: innoing123    時間: 2014-9-29 01:57 PM
Mentor Graphics 與 TSMC 合作為10奈米推出 IC 設計和結束基礎架構 7 P, @) H1 s$ T0 B

' l" s" N: j! P- z! o# _3 g5 c; B 俄勒岡州威爾遜維爾2014年9月27日電 /美通社/ -- Mentor Graphics Corp.（納斯達克：MENT）今天宣佈該公司與 TSMC（臺灣積體電路製造股份有限公司，簡稱台積電）達成10奈米(nm) 的合作協定。為滿足用於早期客戶的測試晶片和IP（互聯網協議）設計起動的10奈米鰭式場效電晶體 (Fin Field-Effect Transistor；FinFET) 的工藝要求，已經改進了物理設計、分析、驗證和優化工具。基礎架構包括 Olympus-SoC™ 數位設計系統， Analog FastSPICE (AFS™) 平臺（含AFS Mega）和 Calibre® 結束解決方案 ( Calibre® signoff solution )。
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6 f9 ]5 g9 C4 g, e, H. _$ nTSMC 設計基礎架構行銷部 (Design Infrastructure Marketing Division) 高級總監 Suk Lee 表示：「TSMC 和 Mentor正在進行廣泛的工程工作，以便讓雙方的客戶都能很好地利用先進的工藝技術。每一個節點都需要進行許多創新才能滿足新的物理要求、提高客戶設計賦能 (design enablement) 的精確度，與此同時性能更優、轉回時間更短。」
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% z. D/ R0 s3 a0 k3 I* KCalibre 提供佈線形狀的全色彩能力，以幫助設計者指定符合10奈米規則要求的設計艙(cockpit)之外的色彩分配。針對制定積體電路佈線圖，改進後的Calibre RealTime 產品能進行互動的色彩檢查，同時利用晶片廠認可的Calibre結束平臺能使用所有制定佈線工具進行設計。
作者: innoing123    時間: 2014-9-29 01:57 PM
針對10奈米  FinFET 設計，Mentor 和 TSMC 還改進了Calibre 填充解決方案。Calibre YieldEnhancer 中 SmartFill ECO 的功能支援「隨時填充 (fill-as-you-go)」工作流，以確保IP和其它設計模組在設計過程中都能準確地呈現。當部分設計被修改時，SmartFill ECO功能可重新填充僅僅受影響的那部分，從而最小化轉回時間 (turnaround time)。同樣的，為在諸如TSMC10奈米這樣的先進工藝節點上維持設計層級實現高效的佈線後模擬， Calibre LVS 也被改進了。 + m3 ]$ `" ?/ k' ^; }' a7 u

* j5 h" Z9 v, `5 ?0 u兩家公司還聯手調整了 Mentor® Olympus-SoC 的佈線和路由系統讓它能滿足 TSMC 的10奈米 FinFET 的要求。為了能用於10奈米 FinFET，數據庫、佈線、時鐘樹合成、提取、優化和路由引擎都做了重大的改進。 " ]# ^% G+ V6 c8 a9 z/ b. l+ C
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為了確保10奈米 FinFET 設備的準確的電路類比，Mentor 與 TSMC 合作讓 BSIM-CMG（伯克利共多柵極電晶體）和 TMI 模型在 Analog FastSPICE 平臺（如AFS Mega）上能用於高速設備和電路層模擬。Calibre xACT™ 提取產品和 Calibre nmLVS™ 產品也支援新的10奈米 FinFET 模型。 2 g9 w% N  m  E9 G
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因Mentor 和 TSMC在設計賦能方面的合作讓客戶取得成功的案例，將於9月30日在San Jose Convention Center（聖若澤會展中心）舉行的TSMC的開放創新平臺生態系統論壇(Open Innovation Platform Ecosystem Forum)會議上講述。瞭解詳情，請參訪TSMC網站 www.tsmc.com 。



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