標題: In your verification flow, the primary EDA vendor/tool your team is using [打印本頁] 作者: sophiew 時間: 2013-9-3 04:14 PM 標題: In your verification flow, the primary EDA vendor/tool your team is using for Verification IP on your current project.- k5 m+ X5 U J1 \" [
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If other (please specify), or you don’t know?作者: amatom 時間: 2013-10-21 01:52 PM
Staff Hardware Based Design and Verification Engineering Lead , p2 y' T9 t' e9 S- B/ Q6 D 5 A* F' J, m6 v公 司：One world top EDA company / @, ?+ q, M( p) R" d$ g工作地点：上海 : p' l( h+ y* s) H" W* K% x G4 S; g
Position Description: : X! \& K& z8 S3 x' _1 ]1. The Staff Hardware Verification Engineering Lead will be in charge of a team of field engineers to support advanced hardware based verification flow integration engagements with Cadence customers and provide easy-to-adopt packages and workshops to xx field application engineers and customers alike. 3 e5 i$ z8 ~3 v9 \0 c6 F. ], r 9 F: z) }% U) @, D# }. y. }2. He/she will focus on the technical aspects of the following hardware verification solutions for customer engagements as well as creating demos/workshops to train field AE and customers: 8 z! ^2 _" B( `( P
(1) xx Palladium HW Acceleration Platforms 4 ^4 _5 ~% e+ b" G9 m- J, G(2) xx Acceleratable Verification IP portfolio 5 r' Y6 {' q, B) G2 J(3) CVA product integration with other xx products such as Incisive Simulation and RTL Compiler for power analysis : [, l4 {4 h3 z0 G# s0 ~(4) HW/SW Co-verification solutions for SoC designs作者: amatom 時間: 2013-10-21 01:52 PM
Position Requirements: - Q7 E# J( a# L( \' U( j1. Experience: 9 ~5 B Y! k5 ~) |+ d6 \- Minimum experience required: 10 years 6 ]4 U3 D( S. a' s- Expertise in RTL top-down design and verification methodology automation are required. This includes full hands on knowledge of writing and debugging Verilog, VHDL and SystemVerilog based D&V environments. 4 v8 p& s$ V; ^2 G0 Y- m& d$ A6 R- We would also like the candidate to have good knowledge of SoC design principles, embedded software development and HW/SW codesign and coverification.. o9 y* Z3 i' V: Y
- Knowledge of UNIX, C/C++, other scripting programming languages ( Perl, TCL…) is highly desired L' k# X1 d+ Y9 P) G8 q/ q. F6 z9 t
- Strong verbal and written communication skills in English are required ; U( n$ b( H& z8 H4 {" x- HW acceleration or In-Circuit Emulation or FPGA prototyping experience is a must & W( r. Q! L$ W/ C+ X- Hardware verification, including knowledge of HDL simulators and debugging simulations - [# f: p6 o& W2 O
- Hands on experience with using design and verification languages like SystemC, SystemVerilog (IEEE 1800) and VHDL is a must.8 q6 k2 W0 m' k' v9 x" o
- Knowledge of embedded systems and software development for SoCs is a plus ) x4 \+ ~1 v7 O, | `$ W: S. y
2. Education: 1 e) c) F1 l0 v" L% I+ P) ?. c9 JIdeally the person should possess the BS/BE level of understanding of CS or EE Engineering concepts 0 x. Q. [. I* ~. _& |- Minimum Education Required: education level of BS with 10+ years experience (or MS with 7+ or more years experience). 7 M* [, \% G! h. m
3. Travel of 30% of the time should be expected.作者: ranica 時間: 2013-11-13 02:37 PM
CAD Engineer% I$ N5 C1 |9 `# ^& f6 H( F
公 司：a top 15 semiconductor company; Q# h7 R; `, i
工作地点：北京$ Q% ?7 r b" `
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Job Description: 6 f, U" @, h6 {) P9 U+ w( Z7 b: o$ P
Collaborate with *** CAD teams to develop industry leading design flows and methodologies for analog and mixed-signal designs using nanometer technologies, with emphasis on improvement of layout productivity of analog circuits, including usage of advanced Cadence IC6.1 features, design for manufacturing (DFM), metal fill, physical verification and tapeout flows. Write scripts and utilities to enhance these design flows. Provide CAD support and methodology training to *** design and layout community. Write application notes and document ***’s analog/mixed-signal CAD flows. Work with EDA vendors to drive ***’s interest with regard to analog/mixed-signal tools. 1 n; Y9 E1 `& B; p2 @* l# B & u# j* f- f6 H* [# P0 hQualifications: 3 @; ~( n6 [: _0 U! v, j
- BSEE or above, with 3~5 years relevant industry experience. $ A+ j; g) p, }+ O' U
- Solid understanding of advanced semiconductor process technologies 3 q# z& n7 L* ?8 @" D) P( N
- In depth familiarity with layout of analog and mixed signal circuits including knowledge of layout effects (i.e. matching, reliability etc.) and DFM rules for advanced technology nodes+ R. |* |& ?5 n5 Z& p) |5 _: J
- Understanding of nanometer design rules and physical verification runsets ' X/ y& @- Y8 O/ M% x& h
- Solid knowledge of Cadence DFII / k) P5 A0 m$ ~6 x/ b/ @# g6 Z6 @- Knowledge of physical verification tools like Mentor Graphics’ Calibre * W' A% B; ]: m, F
- Knowledge of Skill, perl or other programming languages 0 b+ T3 H9 U( H+ U# N; p- Strong written and verbal communication skills作者: ranica 時間: 2013-12-17 10:04 AM
Senior Physical Design Engineer# K- C# w/ k d$ x, _0 [
公 司：A famous IC company Q3 X( j* S- f# F
工作地点：南京9 B& J/ S. L t" M+ }
/ X6 M% l7 j+ u/ Z% dKey Responsibilities 1 M$ E% s' I4 O9 _Depending on experience, key responsibilities will involve some of the following: B n# }$ S0 c1 RIC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification. ' h8 o7 ~5 [/ m* k! o# E4 |As a key member of physical design team, your will work on one of most advanced and the most complex chip designed. ' {; l) [' y- i y! m& oLeading a team of physical design engineers and resolving the technical related issues. ( E/ V. e: ?4 [Crosstalk analysis, power analysis, and static timing analysis. 9 R2 K" C0 _- t2 r) C2 I) d9 \Write scripts in Tcl to improve productivity. $ z4 S. G7 ^4 a9 _4 R
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Experience: 5+ years in physical implementation engineering ) w& \% ]# ?6 D' Z' y# m6 r' j ; s9 d+ Y( R8 q0 g" lEssential skills * N2 J# N( T3 I) V r# \
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills 5 k, f/ ]4 ?; B9 ^
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation. ) E* [- k) E4 g6 R2 W, PGood programming skill. Capable of writing Tcl or Perl. 2 m' v9 h( S1 M# S: i1 Q
Familiar with synthesis, static timing analysis. 8 b8 Y2 V7 F6 D) _
Self-motivated team worker, good verbal and written communication skills in English. 4 n* K6 G7 L) q; v. f5 j1 O7 bTechnical and team leadership proffered. Previous management experience highly desired. 2 h: l& S i8 {9 O( D3 R6 UExperience with synthesis, DFT, and verification is preferred.作者: ranica 時間: 2014-1-23 08:56 AM
Senior/Staff Design Verification Engineer9 G$ n# j, x8 @1 ?. c" [+ T
公 司：A famous IC company & ]% {* {- f, Q. H( l* Y) S( C. b工作地点：上海2 ^6 w1 h" Q6 n/ F
. w3 q% p% f+ Y# ]External Description: $ _6 r- h4 I) C5 k% e8 `- work closely with designers on verification test plan definition and test development 1 B- G/ G1 @4 X- x& J C; k" E- work closely with architects on performance modeling and validation & H& M8 i m) m
- regression infra development 5 f; E! [+ f. |( h0 h, |" \
- coverage analysis and enhancement 2 F4 d/ \2 P$ ?: L
- behavioral model and BFM development . N- w1 \ n; o1 _, H3 {- unit-T and timing gate-level verification 3 K/ S# l4 [( b$ X/ ?- develop IPs verification suites 6 @0 ]% F2 B+ O* ], ^' [- ]. p0 Z
- silicon bring up and debug support C4 Z# p2 M$ z+ @2 D, ?8 _7 A 1 H0 c* t8 T8 J A" a/ n! Z; OQualifications: i8 o: ]9 p$ i
Must have: 4 J7 L1 s @) n1 T$ ?2 _
- minimum 4+/8+ years of ASIC verification experience # B7 J/ ^9 H3 i) i
- BSEE degree or above % k1 K0 z: _5 w; g! _1 B
- strong programming skills, proficiency in C++, system verilog , ]3 ~( q% Z1 V" e9 f* O- working knowledge of scripting language (Perl, Python, etc.) # k( d. P8 Z6 W- working knowledge of verification methodlogies such as VMM, OVM or UVM 5 k' r% x6 B9 t; } I9 b- good communication skill + u$ f$ P' O: g& r- good team work spirit ! \* v* B2 ^ m. w1 V( f3 h" a 3 Z6 Q' c% J3 rNice to have: 6 M# v5 n! n7 f2 x1 F' \- familiar with DTV/STB architecture, design, IP and system作者: ritaliu0604 時間: 2014-6-17 09:54 AM
PLDA和GUC推出一款針對儲存應用進行最佳化、經過測試的可靠PCIe控制器和PHY整合解決方案 - y- r2 |; |& m2 H6 @ + F& a- B# N1 g( p1 I+ r(20140616 17:59:36)加州聖約瑟--(美國商業資訊)--PCI ExpressR IP解決方案業界領導者PLDA和彈性客製化IC領導廠商(Flexible ASIC LeaderTM)創意電子(GUC)，今天宣布推出一款專門針對儲存市場需求進行最佳化的整合型PCIe Gen 3控制器IP和PHY IP解決方案。這款整合型PCIe 3.0控制器/PHY解決方案已進入初期生產階段，並已併入展示板。 # O; u4 |# ~: I9 Y$ ]# {" q/ {9 Z4 c. z
隨著儲存和固態硬碟(SSD)市場的快速成長，客戶專注於降低能耗，維護資料完整性，同時提高效能。PLDA和GUC整合解決方案為PCIe Gen3提供了一款完全整合的矽驗證晶片解決方案，該方案具備儲存應用所需的所有關鍵功能，包括支援更佳的端對端資料保護（採用LCRC、ECRC、ECC、Parity和CRC）、SRIS（Separate Reference Independent SSC）和L1 PM Substates。/ z! P& c5 ]6 p- J2 C" D
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PLDA XpressRICH3 IP是一種高效能、低延遲、高度可設定的PCI Express 3.0軟IP，支援端點、根埠、交換器和橋接器組態。此外，PLDA IP具有各種先進功能，例如SR-IOV、多功能、multi-VC、ATC、TPH、PASID、ECRC、AER等，並符合PCI Express 3.0修訂版規範。PLDA的PCIe 3.0 IP還提供符合業界標準的XpressRICH3-AXI版AMBA AXI4介面。作者: ritaliu0604 時間: 2014-6-17 09:54 AM
GUC的PCIe Gen 3 PHY專為滿足儲存市場的需求而設計。採用GUC成熟的高速SERDES技術，GUC PCIe Gen 3 PHY的效能超過了PCI Express基本規格參數3.0修訂版，同時完全符合BASE和CEM規範，並支援適合儲存應用的SRIS（Separate Reference Independent SSC）和L1 PM Substates等功能。- D" [: ]% g& v5 _' H7 I' v
5 A ]: ~8 l% M2 P" S& [為了提供更完整的PCIe及其儲存應用優勢概覽，PLDA撰寫了一份名為《征服PCIe和NVMe挑戰，發布最具競爭力的企業PCI SSD》的白皮書。這份白皮書可以從PLDA網站www.plda.com獲得，它對PCIe為何是儲存和SSD領域設計者的一大優勢提供了一個深度技術解答。 4 K6 ]# r. w; R; A. @9 S 2 ~# z% [' X5 n" ~供貨 9 c! p* y2 A# ?, \9 G1 ]9 W; e5 p) R" t
PLDA現已發售PLDA XpressRICH3 IP。GUC現已發售PHY IP。 5 w! F- m* y3 E) K# ^# o* x: Z) s. W) J' u4 ?
PLDA PCIe 3.0控制器和GUC PCIe 3.0 PHY整合解決方案的單晶片評估板現已可供評審。請聯絡PLDA以索取一份評估。 $ ~; }% n$ r+ [9 q+ l. o0 l0 r 0 G- |* k) ?8 O. q) N7 ~) g' F關於PLDA . C* D9 w$ l( m, Q% G: [PLDA設計和銷售ASIC和FPGA核心智慧財產權(IP)及原型設計工具，為嵌入式電子設備設計者加快產品上市時間。PLDA專門研究高速介面協定和技術（如PCIe）和乙太網路。PLDA提供擁有一整套工具的IP核心，包括可隨時投入生產的FPGA原型設計卡或模組系統元件、驅動器、應用程式介面(API)和測試台。該公司的產品受惠於一個全球支援和銷售組織，該組織能夠在全球支援 5,800多家ASIC和FPGA客戶。PLDA是一家跨國公司，在北美（加州聖約瑟）和歐洲（法國、義大利）設有辦事處。如需詳情，請造訪www.plda.com。作者: ranica 時間: 2014-7-11 10:26 AM
IC CAD 工程师: T' T r0 t& p. [
roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills 5 k, f/ ]4 ?; B9 ^