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$ L5 g3 V! P3 i9 z1 |; l | | 09:30-09:40 | Welcome Speech | | 09:40-10:10 | Guest Keynote - Dr. Kuo Wu, Deputy Director of Design Service Division, TSMC | | 10:10-10:40 | Keynote - Daniel Yang, PacRim Managing Director, Mentor Graphics | | 10:40-10:50 | Break | 10:50-11:25 8 g6 c) j- ?3 W) H+ r& a5 L6 O
 | | Improve Your Productivity with Calibre TVF | 議程說明  3 v8 h$ ?% } ?- ? ^
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In the nano-era, physical verification becomes much more challenge. Not only because the number of design rules explodes dramatically, there are also a lot of new problems we need to handle such as the manufacturability issues. Mentor provides Calibre TVF (Tcl Verification Format) for use in coding Calibre rule files. It could help you to reduce the effort of rule file creation and maintenance, and also help you easily customize your rule checks. In this paper, we would like to share some of our experiences of Calibre TVF. Let’s enjoy TVF, now.
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3 I A3 j& u4 S) m1 A | | 11:25-12:00 | | Dramatically reducing DRC run time by using Incremental DRC |
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- W( }- E' W% CIn nanometer technology, thousands of design rules will be checked and more and more iterations will be requested before signoff our design. The DRC run time could be dramatically increased from couple of hours to couple of days. Think about this, if you can real time get the DRC results and then correct those errors with the instruction of Calibre DRC to avoid creating new errors before the whole design DRC finished, waiting will not be the only thing you can do. Calibre incremental DRC inclues complete flow, design delta flow and previous result flow to provide more convenient and easier GUI to achieve the reduction of DRC run time in different purposes. We would like to introduce the concept of Calibre incremental DRC and share some sucessful experiences in ruducing our DRC run time by using Calibre incremental DRC and also some suggestions that need to be improved.
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| | 12:00-13:30 | Lunch | | 13:30-14:05 | | Macro Model vs. Calibre xRC | 議程說明
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1. Macro Model in VIS & k2 Z" s4 Q. K( e
2. Why to use Macro Model
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9 E' H" a+ S2 n6 O0 P4. Customers' concerns in Macro Model5 D! v1 [/ N% ?+ C' t8 o# I
5. Conclusion 8 s% ?0 }2 I9 f$ ?4 Y, U4 J
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| | 14:05-14:40 | | Review of post OPC checking; Why do we need post OPC check? | 議程說明
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| | 14:40-15:15 | | Application and Yield Estimation - Using Calibre Yield Analyzer for Critical Area Analysis in Layout | 議程說明
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Application and Yield Estimation - Using Calibre YieldAnalyzer for Critical Area Analysis in Layout Critical Area Analysis estimates random defect impact on a design, which becomes more sophisticated compared to other DFM fields in these days.) S% M3 ^0 c- R8 w5 F
On the other hand, to have a methodology which can estimate design quality in manufacturing aspect becomes a strong demand from fabless IC design houses.
n S9 b0 X- OThis presentation introduce UMC's experience for Mentor Calibre YieldAnalyzer CAA. We are glad to share with everyone and exchange ideas and thoughts by this opportunity. And we are going to present a practical CAA system and share the experience regarding how we build up the system. It includes fab data calibration, model selection, cell-level CAA, and service flow setup. With comprehensive index generated by the system, IC design houses can assess the random defect impact on a product, proceeding neceesary enhancement or forecast. ( J. @5 H }2 X4 L; O, F5 B+ F2 `
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" B: R8 t4 _' a3 _3 o2 s | | 15:15-15:35 | Break | | 15:35-16:10 | | ADiT VPI Application on Thermal Sensor | 議程說明
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| | 16:10-16:45 | | At-speed Test on a Design with Multi-clock Domain | 議程說明
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At-speed test is becoming more and more popular, and handling multiple clock domains and pattern number reduction are two of its challenges. This paper describes a case study of how Mentor Graphics TestKompress was used successfully on a large video chip with 5 different clock domains to test for both transition and stuck-at faults. On-chip modified PLL clock generation circuit and individual clock enabling/disabling scan cell are used to control the multiple clock domains during at-speed testing. In addition, some features of TestKompress like mode definition in the test procedure file and merger flow are shown in this paper, which are used to reduce the pattern number while maintain the test coverage. 3 I( ]- ~% M' s1 ?
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| | 16:45-17:20 | | Methodology for Improving Scan Diagnosis Resolution of Bridging Defect | 議程說明 - t4 ^" {. _& x
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The goal of this paper is to improve scan diagnosis resolution of bridging defect by finding possible net pairs within a design which are likely to have bridge defect and generating patterns for bridging candidates. The flow mentioned here-in includes net pair identification with Calibre, deterministic bridging ATPG with FastScan and TestKompress, and scan diagnosis with YieldAssist. Test vehicle is a real design in silicon on 90nm technology node, with manual bridging fault injection, the actual fault can be correctly identified with high confidence score. , t% ]# o' k7 H" }& ?
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| | 17:20-18:30 | | | 18:30-20:00 | |
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