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標題: 關於cell-based 流程的DRC問題 [打印本頁]

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作者: ywchywch    時間: 2008-3-7 02:22 PM
標題: 關於cell-based 流程的DRC問題
請問各位大大
) ^7 M4 T  s" @. ]我用TSMC18的design kit作cell-based layout的練習，軟體是用encounter，大部分的步驟是依照CIC所提供的Lab去做，完成之後用我的GDS檔去做DRC，會出現下列的DRC ERROR，而且是M1~M5、via1~via5都會有這方面的error，因為error的數目頗大，不太可能用人工去debug，所以我想請問有經驗的大大們，能不能告訴我最大的問題點在哪裡？以及這些錯誤代表什麼？要如何debug比較適合？

6 w/ P/ D8 ~6 ~( o2 j  q先謝謝各位大大了!!感激不盡!!
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+ U$ w4 P) D: c9 J1. M2.W.1 { @ M2 width < 0.28
  INT M2 < 0.28 SINGULAR REGION ABUT < 90
}

2. M2.S.1 { @ M2 spacing < 0.28
: h# [6 A1 E4 s  EXT M2 < 0.28 ABUT < 90 SINGULAR REGION
}

6 B9 q2 R; b' \, N3. M2.S.2 { @ Wide M2 (>10um) min. to M2 < 0.6 um
  M2_S5 = SHRINK (SHRINK (SHRINK (SHRINK M2 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5
  M2_G5 = GROW (GROW (GROW (GROW M2_S5 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5
3 U( M4 l8 @! I7 D9 b, `- }# v  M2_Wide = M2_G5 AND M2
5 \% {( K% R# C9 V
  M2_Exp = SIZE M2_Wide BY 1 INSIDE OF M2 STEP 0.196
7 J( n+ v4 F' K1 F! A8 s* m/ u  M2_Branch = M2_Exp NOT M2_Wide
* E1 a3 m2 Z- l) v/ _! U0 G  M2_Branch_edge = M2_Branch COIN INSIDE EDGE M2
3 ~6 b5 j# t: @1 n  M2_Check = M2 AND (SIZE M2_Exp BY 0.6)
  M2_Else = M2_Check NOT INTERACT M2_Exp
! |9 @3 Y! \; |- z  M2_Extend = M2_Check NOT M2_Exp

  EXT M2_Wide M2_Else < 0.6 ABUT >0 <89.5 REGION
% C! p4 ^& H8 |# h# P+ @  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 OPPOSITE REGION
7 A  K- y% D! y3 _9 ?: h/ p  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 CORNER REGION
  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 PROJ==0 REGION
9 f0 K9 J! U# p: L* S' `  A = EXT M2_Exp < 0.6 ABUT > 0 < 89.5 SPACE REGION
# F, I5 l# G" l3 r& m4 A% F6 [( a  A NOT INTERACT M2_Extend
, G! Y5 z! v! _8 C' G* q2 C}
1 w3 T: S  E+ e' r4. M2.E.1 { @ Min extension of a M2 region beyond a VIA1 region is 0.01 um
   ENC VIA1 M2 < 0.01 ABUT<90 SINGULAR
1 M4 r0 d; l- Y8 O7 c5 H4 ~   VIA1 NOT M2   
$ D% E* e# `6 Q9 \7 F}
, i3 T  Q  L+ O7 w; A
5. M2.E.2 { @ Min extension of M2 end-of-line region beyond VIA1 region is 0.06um
% O2 b# b. q- K: c- m* ~3 |2 T   X = ENC [VIA1] M2 < 0.06 ABUT < 90 OPPOSITE                // a narrow side
   INT X < 0.26 ABUT == 90 INTERSECTING ONLY       // adjacent narrow sides
0 Q1 J. X2 o: v% _- {1 |}
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6. M2.A.1{ @ Min M2 area region < 0.202
  AREA M2 < 0.202
9 O6 v$ f! U$ h. e, _' y8 S6 k}
// Density check M2.R.1 included at the end of this file
$ W5 {" Q! k7 G6 Y9 ~# \6 r' ?// VIA2 checks
$ S. f) V) q5 \! C//=============
: D2 }. }8 k. t1 p5 G( O6 w  G
7. VIA2.W.1 { @ VIA2 must be 0.26 x 0.26 um
  A = NOT RECTANGLE VIA2 == 0.26 BY == 0.26 ORTHOGONAL ONLY
  d) V( [2 U/ f1 E3 L  A OUTSIDE RNGX   // exclude from metal fuse protection ring area
* G& S7 l3 G) O) y! P}

8. VIA2.S.1 { @ VIA2 SPACING < 0.26
, b5 i5 I7 Z2 M* V! X: h  I  EXT VIA2 < 0.26 ABUT < 90 SINGULAR REGION
}

* a/ e: c% S" `9. VIA2.E.1 { @ Min extension of a M2 region beyond a VIA2 region is 0.01 um
  ENC VIA2 M2 < 0.01 ABUT<90 SINGULAR
) l: L  A- a9 l' e- b  VIA2 NOT M2   
% K. c2 K# h% @8 L: z8 v. z( S$ M, x}
( ?. T4 u" N$ e1 @; z' k, o
* f9 z, T$ ]* s4 C10. VIA2.E.2 { @ Min extension of M2 end-of-line region beyond VIA2 region is 0.06 um
- K9 B% ]4 ~4 Y7 c4 S. X1 q   X = ENC [VIA2] M2 < 0.06 ABUT < 90 OPPOSITE         // a narrow side
6 J" |2 _6 Y. L   INT X < 0.26  ABUT == 90 INTERSECTING ONLY     // adjacent narrow sides
}

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作者: motofatfat    時間: 2008-3-7 02:30 PM
我猜你試用APR軟體RUN出來ㄉ
* ~' V1 o9 B1 C0 I4 w& q9 d應該是相同NET ㄉMetal space 和 via extension
不夠的問題,通常會用 skill file 來修正

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作者: michael6172    時間: 2008-3-7 02:51 PM
我覺得你打電話去CIC問工程師會比較快吧 ...

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