標題: RF CMOS power cell layout [打印本頁] 作者: rfbeginner 時間: 2008-4-23 07:22 PM 標題: RF CMOS power cell layout Now I'm involving some CMOS PA design, adn when I design CMOS power cell, when I use the tranmission line mode (ADS), everything looks like OK, but when I repalce this ADS lines with EM simulations, I found that the gain distorted a lot becasue of gate line, but drain line will not be affected, I utilize the DOngbu 013 um model, but this case will not happen on TSMC018um, who can expalin something? thanks a lot. 5 ]& }6 \1 K7 k5 _: @6 s# } 6 i; h' K: e& |0 s5 {+ lBesides, I found that if I set the conductivity of substrate=0, the gain will not distort and is similaor to ADS result