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09:00~09:30 / Registration9 Z- x* P$ t" N" I1 C
; X: K) [8 R' c8 Q% d. w8 Z09:30~09:40 / Automatic floorplan for design exploration to get the best result 9 U! G+ J- N8 T- J7 l. F - F. ?7 F! ~ k, O2 J09:40~09:50 / Balanced clock tree to reduce process variation effects 6 T% o5 H, E) r, S % O! t) A6 k- v* r09:50~10:00 / 32nm support for the very advanced technology / t C6 h5 q) J* A; _; W2 j) E& M
|0 Q4 `; x5 d" p( M! P10:00~10:10 / Post route optimization and SI closure productivity / L9 U+ D1 _8 G
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10:10~10:20 / 100% MMMC support in the entire implementation flow ! ^+ J$ I3 i+ Q( c" @5 w1 f: I6 g' p4 G( G
10:20~10:30 / Dynamic power optimization and low power CTS for power reduction v- R" }' H0 I8 K 6 k- ?. _, {, S4 E ( s% H9 I2 e& V. n. k( E
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10:30~10:50 / Break ) z8 P, ~4 S7 U. [
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10:50~11:00 / Encounter Power System for new generation power integrity analysis 5 G1 v& a q2 S- D; }) m* l$ `( U
8 }, e0 o9 Y% k11:00~11:10 / 3 very advanced statistic applications for better performance 6 C$ \1 R8 V r: q
6 A, }8 Z* R5 q! W1 W* q. l11:10~11:20 / Active Logic Reduction Technology (ART) to handle big chips ( j7 A1 ?% ?; u: x, T$ h " W# Z% K+ w& x2 v2 s 5 f' x* l x, L" d: T6 c
0 i( U. N' U6 c d6 }3 N) H" T11:20~11:30 / Constant run time and memory usage improvements 3 x. i, p6 ~- v! B2 X+ r+ g4 f & |- s5 ^/ k( K11:30~11:40 / End-to-end parallel computing support + ?' w! |' s6 z# _' U $ T# @! H# ]; v8 W3 @11:40~11:50 / Encounter Foundation Flow for ease of use and productivity gain3 t0 D4 z8 @+ P; e4 O
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11:50~12:00 / Ending / k/ B5 W0 Z% } 9 w. k' s& u' D: \ s: u5 R5 E12:00~13:30 / Lunch