EDA戰雲密佈！RD戰力分析？ - Chip123 科技應用創新平台

台灣再度成為3大電子設計自動化（Electronic Design Automation；EDA）業者角力戰場！繼新思（Synopsys）台灣研發中心擴編進度超前，益華（Cadence）在新任總經理張郁禮帶領下，規劃將台灣研發中心人員擴充1倍以上，全力搶攻台灣新思旗下客戶群並開發前端科技新興市場，誓言奪回市場寶座；據了解，明導（Mentor）同時也規劃第三季將設立台灣研發中心，並延攬台灣新思研發中心主管劉樂群領軍，3大EDA業者本土戰雲密佈！
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- m% z/ B' w6 p- M9 ^6 V$ i6 Q　益華目前除了5大產品平台：Incisive、Encounter、Virtuoso、Allegro及DFM外，每年更以龐大研發資源投入先端半導體技術設計，台灣行銷總監馮元掄表示，目前益華與各大晶圓廠包括整合元件（IDM）及晶圓代工業者、設備業者及設計公司共同合作的X-Architecture逐漸被市場接受，並從90奈米演進至65奈米製程技術，應用層面也從PC繪圖晶片擴散至網通領域；同時，益華積極與台面板廠共同開發SoP（System on Panel），將傳統SoC設計手法套用在面板系統電路設計上。
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　不僅益華重新調整台灣市場策略轉趨積極，據了解，明導近期也展現台灣市場佈局大動作，不但延攬新思研發中心高階主管劉樂群，同時規劃在第三季宣佈設立台灣研發中心，也使得3大EDA業者在台灣研發中心已全數到齊。儘管新思全球營業額僅次於益華，不過，新思紮根台灣坐擁第一的位置，已成為益華、明導等業者亟力拿下的目標。

6/30/2010	SiS Adopts Cadence Technologies for Advanced SOC Designs
6/21/2010	Cadence Completes Acquisition of Denali
6/14/2010	Cadence Delivers Extensive Support for TSMC AMS Reference Flow 1.0 for 28-nm Process
6/14/2010 + R0 S- _2 s' k9 g	Cadence Delivers TLM-Driven Design and Verification, 3D-IC Design and Integrated DFM Capabilities to TSMC Reference Flow 11.0
6/14/2010	Cadence Kick-Starts UVM Adoption with Open-Source Reference Flow Contribution to UVM World
6/11/2010	Cadence Announces Comprehensive SOI Design Hub
5/24/2010	Cadence and IBM Team to Develop Leading-Edge IP
5/24/2010	Rapid Bridge LiquidIP Now Available as Part of Cadence Open Integration Platform
5/20/2010	Computer Simulation Technology Announces Closer Cooperation with Cadence
5/14/2010	Cadence to Acquire Denali
5/7/2010	Cadence Accelerates SOC Realization, Reduces Costs with New Open Integration Platform
5/3/2010	VIA's Centaur Achieves Significant Benefits Using Cadence Virtuoso Space-Based Router at 65nm
4/26/2010	Cadence Debuts Verification Computing Platform
4/21/2010 $ {. v9 Y: q2 J4 V5 @8 f	Cadence Contributes Technology to Boost Verification of Complex Mixed-Signal Chips
4/14/2010	HiSilicon Adopts Cadence Mixed-Signal and Low-Power Technologies
4/14/2010	LSI Adopts Broad Range of Cadence Mixed-Signal Technologies
4/14/2010	TSMC Expands Cadence Tool Support In Integrated Sign-Off Flow By Adding Synthesis, Place and Route, and RC Extraction
3/29/2010	Cadence Teams with AcAe to Accelerate Transition to Allegro PCB Products
3/24/2010	Renesas Cuts Design Time by Half on Large-Scale Consumer SOC by Using Cadence Encounter Technology
2/2/2010	austriamicrosystems Expands Reliance on Cadence Technology to Achieve Seamless Mixed-Signal SOC Designs
2/2/2010	Cadence EDI System 9.1 Addresses Productivity Crisis for Complex SOC Design
2/1/2010	Cadence Software Validated on STARC QA Database
1/27/2010	Renesas Adopts Cadence Virtuoso Technology for Mixed-Signal and Analog Design
1/25/2010	Cadence OVM SystemVerilog Solution Enables More Thorough Verification at Mitsubishi Electric
1/25/2010	NEC Electronics Adopts Cadence Encounter Digital Implementation System for 40-nm ASIC Designs

Mentor Announces Commercial Linux Platform for Freescale Processors Based on Power Architecture Technology	6/23/2010
Mentor Graphics Questa Functional Verification Platform Adopted by Mindtree	6/21/2010
Mentor Graphics Extends TSMC Reference Flow 11 with Support for ESL and Integrated Design and Manufacturing Closure	6/17/2010
Mentor Graphics' Olympus-SoC Place-and-Route System Now Supported By X-FAB	6/17/2010
Mentor Graphics Provides Comprehensive Verification Support in TSMC AMS Reference Flow 1.0	6/17/2010
Mentor Graphics Working with TSMC to Speed SOC Verification with Calibre Automatic Waivers	6/11/2010
Mentor Graphics Announces Calibre xACT 3D for Fast and Accurate Extraction Using 3D Field Solver Technology	6/8/2010
Mentor Graphics Underscores Support for OVM and Extends Support to UVM Across Multiple Products	6/7/2010
Mentor Graphics Introduces Precision Rad-Tolerant Product for Advanced Radiation Effects Mitigation	6/3/2010
Mentor Graphics 0-In Formal Version 3.0 Brings New Level of Automation to Formal Verification	6/1/2010
Mentor Graphics Releases 0-In CDC Version 3.0 to Support Verification Needs of Larger, More-Complex Designs	6/1/2010
Mentor Graphics Announces New FPGA Synthesis Innovation in Precision Synthesis 2010a Release	5/20/2010
Mentor Graphics and NetLogic Microsystems Establish Strategic Multi-Core Collaboration for Embedded Linux	5/19/2010
Valor Releases Major New Functionality In the vSure DFM Product	5/19/2010
Mentor Graphics Veloce Delivers 400X Acceleration for OVM Driven Verification	5/7/2010
Mentor Graphics Calibre InRoute Delivers True Manufacturing Sign-Off During Physical Design Closure	5/3/2010
Mentor Graphics and Lauterbach Collaborate On Hardware-Accelerated, Software Development and Debug Platform for SOC Verification	4/27/2010
Mentor Graphics Selected as a Key Freescale Commercial Linux Strategic Partner for QorIQ and PowerQUICC Processors	4/26/2010
Mentor Graphics Announces Multicore Solutions for Symmetric and Asymmetric Multiprocessing	4/22/2010
STMicroelectronics Adopts Mentor Graphics Veloce Emulation Platform for Its New Generation of Set-Top-Box Chip Sets	4/15/2010
Mentor Graphics Extends DO-254 Platform Offering with Enhanced HDL Coding Standards	4/14/2010
Mentor Graphics ReqTracer Automates Requirements Tracking and Reporting for Electronic Design Projects	4/5/2010
Mentor Graphics and Platform Computing Optimize Use of Veloce Emulation Systems as Shared Resources	3/30/2010
SMIC Bases DFM Sign-Off Strategy on Mentor Graphics Calibre Platform	3/30/2010
Mentor Graphics Calibre LFD Certifications at TSMC Now Include 28-nm Process Node with TSMC UDFM Engine	3/23/2010
The MathWorks and Mentor Graphics Outline Joint DO-254 Workflow for Model-Based Design	3/23/2010
Mentor Graphics Acquires Valor Computerized Systems	3/18/2010
Mentor Graphics to Extend Cooperation with STMicroelectronics for Advanced Chip-Development Design Solutions	3/16/2010
Mentor Graphics Adds AMBA 4 Verification IP to the Questa Multi-View Verification Components Library	3/10/2010
Mentor Graphics Introduces FloTHERM IC for Semiconductor Package Thermal Characterization and Design	2/25/2010
Dongbu HiTek Adopts Mentor Graphics Eldo for Optimized Cell Characterization Flow	2/23/2010
Mentor Graphics Eases Android Development with Support of Inflexion Graphical User Interface on the Zoom OMAP36x-III Mobile Development Platform	2/15/2010
Mentor Graphics Enhances Signal and Power Integrity Solution with Full-Wave 3D Analysis	2/3/2010
Agnisys Announces Support for OVM Register Package in IDesignSpec	2/1/2010
Mentor Graphics Catapult C Adds SystemC Synthesis and Expands Full-Chip Capabilities	1/25/2010

SVTC Technologies Selects Synopsys' Manufacturing Tools to Accelerate Time to Commercialization	7/14/2010
Open-Silicon Integrates 50 DesignWare Interface and Analog IP Products with 100% Silicon Success	7/7/2010
ARM, IBM, Samsung, GlobalFoundries and Synopsys Announce Delivery of 32-/ 28-nm HKMG Vertically Optimized Design Platform	6/17/2010 ! L/ e6 ~% i8 }7 S
PrimeTime 2010 Scales Timing Analysis Beyond 500 Million Instances	6/17/2010
Synopsys Delivers Optimized Lynx Design System for Common Platform 32/28-nm Technology	6/17/2010 & b# J+ U4 U# B
Synopsys Unveils Galaxy Characterization Solution for Standard Cells, Complex Macros and Memories	6/17/2010
Synopsys Unveils StarRC Custom 3D Extraction Delivering 20X Speedup	6/17/2010
Synopsys Delivers Comprehensive Custom Design Solution for TSMC Analog/ Mixed-Signal Reference Flow 1.0& B9 _$ v: F2 G$ S$ V2 d9 K K	6/11/2010 / ^7 L( T% a1 H* Y3 r& s
Synopsys to Acquire Virage Logic ; g) z n O) U/ _% V1 N	6/11/2010 & \|/ S% p. C! A" ?- e1 w
Synopsys and IEEE-ISTO Launch Technical Advisory Board to Evolve Interconnect Modeling Standard 3 m) k: i3 E# O, a. u7 N8 `( @	6/7/2010 5 q; _8 K) b5 c0 s9 ?% p; A$ c
Synopsys Announces Synphony HLS Support for Xilinx Virtex-6 FPGAs ) {! {* K& k0 t: ^	6/4/2010 # K& T- j8 K+ f9 d/ ~0 b2 F
Synopsys Press Publishes "The Ten Commandments for Effective Standards" 5 ?) W; b3 C; q	6/4/2010 , r0 g$ q% V6 Z! h0 s) G# A5 B$ c
Synopsys Collaborates with SMIC to Deliver USB Logo-Certified DesignWare USB 2.0 nanoPHY in SMIC's 65-nm LL Process Technology 6 _' w* y4 x) k o	5/13/2010 ' W3 E% _( I. e/ O. Q8 T1 i
Latest Synopsys IC Compiler Release Delivers More than 2X Speed-Up, Enhanced In-Design Technology and Production Support for 28/32nm 5 }( C8 a6 I+ ^; E/ v% r( N	5/7/2010 , f0 Q- c7 {% U# j
Synopsys Unveils Ethernet Controller IP with New Audio Video Bridging Feature . j, r' d" c/ y! a$ g	5/7/2010 - B% I$ \|, a- N0 S' @1 R9 {
Synopsys Launches Industrys First MIPI DigRF v4 IP % l. r4 ~" ]# W6 y2 q	5/3/2010 9 f& @7 c0 _$ z. e# t
New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces $ V# K- v, e0 k1 V8 w3 V' f% l	4/28/2010 ! S& A# k9 j7 Q; V' B% Y0 p
Synopsys Announces Support for Actel's New SmartFusion Intelligent Mixed-Signal FPGAs : z. e) m% f1 Y7 Q+ E	4/22/2010 7 {- l$ z- P' n. D0 a9 D
Synopsys Introduces the HAPS-60 Series of Rapid Prototyping Systems * f4 M4 U+ W6 @ {	4/19/2010 - h. N u3 p+ D. v, U& M
Synopsys Expands IP OEM Partner Program with Two New Members * ^ M, b3 e' [ J	4/14/2010 2 l/ V! e9 q3 K- \|
Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards In a Single PHY $ N5 ?- A+ k- K& P4 _	4/7/2010 * X1 I Y# C" B- G/ h" c
Synopsys' DesignWare SuperSpeed USB 3.0 IP Receives USB-IF Certification , \|: X6 m% u3 n$ h	4/5/2010 0 v: j8 h8 m. [+ G8 m9 }8 J
SiliconBlue Selects Synopsys as FPGA Synthesis Partner for Its iCE65 mobileFPGA Family 0 y* ~5 Q$ s2 S7 ~! }	4/1/2010 3 r. G3 j+ k3 X3 J. g) B
Synopsys Galaxy Implementation Platform Enables First-pass Silicon Success on Infineon's 40-nm X-GOLD 626 Wireless Product 6 [2 D4 G4 J& b6 d$ q3 v	3/30/2010 & Z9 [* i/ l- m
Design Compiler 2010 Doubles Productivity of Synthesis and Place-and-Route " x. ^: w4 n. c1 F @	3/29/2010 ! [+ ]( }3 ]# G: H
Nationz Technologies Achieves First-Pass Silicon Success with CustomSim Mixed-Signal and VCS Functional Verification Solutions 3 w# o0 ]& N) c	3/23/2010 + g8 Y1 P/ W+ I) L
Renesas Technology Adopts Synopsys Proteus OPC for 28-nm Development / `% G$ D. k9 i3 M, T5 {+ T	3/23/2010 $ h# Q0 _$ A$ l" {( N3 n/ f, P
Synopsys Completes Acquisition of CoWare - @3 P$ i' X8 j6 K- u& G	3/23/2010 9 o% d6 V K6 y7 o. H1 a! v1 k- U
IMEC and Synopsys Collaborate on 3D Stacked IC Development " h% @' O7 n3 f1 J	3/10/2010 : o) a- M) `. K& q' }
Synopsys Galaxy Custom Designer Accelerates Analog/ Mixed-Signal Engineering Productivity with Built-in DRC Visualization and Correction & f; h$ C& B/ {6 _	3/10/2010 7 h7 X7 I8 T- M
Yamaha Tapes Out Graphics Chip with Synopsys Design Compiler Graphical 7 h& h2 c/ d0 T& t	2/9/2010 9 ^, d0 M: r; G& ]
APAC IC Adopts Synopsys Galaxy Custom Designer Solution for Analog/ Mixed-Signal IC Design Services # I+ ~. V; f: _, Q3 a# g	2/8/2010 ; w0 Z2 S& n I+ q0 \|
Synopsys to Acquire CoWare / s) \|& [2 X1 Y0 Q' t	2/8/2010 1 }; C$ a3 S7 N3 a5 U. r. s% A
Synopsys Acquires VaST Systems Technology 1 k! S1 [3 ^& {* M	2/3/2010 9 e( l. k7 y, r$ { a2 [
Synopsys Expands DesignWare IP Portfolio with MIPI IP Solutions $ Z2 s& j& S1 f1 ]0 @, X7 c! a	1/25/2010 % t# o) R% x; y( L- `; L
Synopsys Launches DesignWare HDMI 1.4 Tx/Rx Controller and PHY IP Solutions for 40-nm Process Technologies / m' ^/ w) v. \- q	1/25/2010 0 a7 z" e: R+ y1 \|# ]6 P
Toshiba Information Systems Standardizes on VMM-LP Low-Power Verification Methodology ' k( \+ R+ J6 Q& q	1/25/2010 * \* I, R" C7 y/ ~
Synopsys Announces DesignWare Protocol Analyzer for Verification of SuperSpeed USB 3.0-based Designs ) F' e6 B: X+ ~! `5 g1 K, z! b	1/13/2010 8 g6 r: g' t: U9 R! \|7 \|' o
Synopsys Introduces SystemC TLM-2.0 SuperSpeed USB 3.0 Models ( {. \| V% G+ X4 P7 F- O	1/12/2010 F( G# x2 q+ O- O& I% h+ a
Synopsys Multicore Technology Speeds Timing Sign-Off by 2X ( U9 ~7 u: i1 L" S* m. Q	1/11/2010