時間 : 2007年1月24日(星期三) 下午1:00 -- 5:30
地點 : 新竹科學園區科技生活館202室 (新竹科學園區工業東二路1號)
費用 : 免費入場，備有茶點
主辦單位 : 宏太科技 (Avant Technology Inc.,http://www.avant.com.tw)
協辦單位 : 台灣SoC推動聯盟 (Taiwan SoC Consortium)
報名 : 請至http://www.avant.com.tw/chinese/seminar.htm 報名
抽獎 : 參加者有機會抽中高級數位相機一台, 請攜帶名片參加抽獎
研討會議程 演講主題 演講摘要
13:00 –13:30 Registration
13:30 –14:20
Architectural considerations for cool designs: Strategies and implementation techniques for embedded memory IPs to minimize power consumption and achieve the most optimum performance and cost
Cyrus Afghahi, CEO, Novelics
Farzad Zarrinfar, President, Novelics
The rapid expansion of feature-sets in consumer products such as cell phones and portable multimedia solutions is pushing the limits of embedded memories. Price pressure, the need for differentiated features with balanced power/performance, data security, and dealing with minimum IP suppliers are forcing chip designers to evaluate emerging memory techniques for their designs. This section introduces compiler-driven 'Cool' and 'zero-leakage' Memory IPs include coolSRAM-1T, coolSRAM-6T, coolOTP, coolReg, coolCache, coolCAM and coolROM for low power, and high performance ASICs, ASSPs, and SOC designs. These IPs are implemented with standard logic CMOS process with no additional masks or process steps to minimize cost, as well as maximize reliability and portability.
14:20 –15:10
Manufacturing Induced Variation Aware Design In 130nm And Below
-DFM/DFY-
Darren M. Tay
President/CEO, Nanno SOLUTIONS
Won-Young Jung
Executive VP/CTO, Nanno SOLUTIONS
As scale goes down to 130nm and below, interconnect is getting more dominant and significant for design performance. However, designers consider device worstcase models for both verification and characterization of circuit performance. They typically do not include interconnect worstcase model in their analysis because the impacts of interconnect related process variations cannot be decided in worstcase model. Recent efforts have been attempted in determining interconnect, worstcase of statistical approaches. Despite of the efforts, these methods fail to accurately predict an interconnect worstcase model, which has non-normal distribution, and the methods are time-consuming when used to generate the models. This seminar will discuss a new design environment to provide the interconnect worstcase model/DB based on a statistical algorithm with accuracy and efficiency. It will also introduce state-of-art DFM/DFY solutions which are provided by Nanno SOLUTIONS, Inc.
15:10 –15:30 Coffee Break
15:30 –16:20 Bridging The Verification Gap
Stephen Scholefield
CEO, TransEDA
Coverage Analysis in the Design Flow
Practical Value of Coverage Analysis
Coverage Measurements and their Practical Value
Practical Coverage Directed Verification Methodology
Managing and Optimizing the Test Suite
Case Study
16:20 –17:10 SoC設計的自動化驗證
Thalia Ko Manager, 宏太科技
以Assertion為基礎形式驗證是一種常用來對SoC數位電路進行功能驗證的方法。與動態式的解決方案相較，雖然此一技術具有多項優勢，但也有一些缺點，使其只能侷限於具備驗證專業知識的專家所使用。因此，為使形式驗證能發揮更佳的效益，業界致力於將其予以自動化作業以及與模擬技術平滑整合。
Aerielogic將展示以下幾個功能驗證領域是可以透過自動化形式驗證來取得更大的效益：設計覆蓋增強、協議相容檢查，以及功能效能分析。利用Aerielogic的設計方法，不論是設計人員或驗證工程師都可以輕鬆地達成這些工作。