& e& o7 w+ s+ I: x j; ^1 ]Finalists were judged according to the following criteria: 8 G* G/ u- z' Y6 T●Innovation 7 I5 p7 }- p2 M8 X4 |$ N/ K# C: D2 Z
●Uniqueness % c: `6 j6 W2 H$ G- m1 D●Market Impact + c7 r O) F! B, d7 N L
●Customer Benefits . \ I `6 v" Q
●Value to Society : N! T0 M. ?" A: @' v
% \1 V' x! u1 l* nDesignVision Awards Finalists $ [8 C# l& c) t7 s% n+ FIn each of the nine categories, the 2007 award finalists include the following companies and products respectively: 4 q4 T( N) y c; t5 c( q5 g: J" Y8 `7 V4 Z
ASIC and IC Design Tools Q( T* z4 t4 K7 t$ ` ●Cadence Design Systems, Inc. – Cadence Space-Based Router * Z" T6 Q+ N1 R6 z ●Mentor Graphics Corporation – Calibre LFD 9 u* g) j6 b" X/ c$ w ●Novas Software, Inc. – Siloti(tm) Visibility Enhancement (VE) family 0 H& x6 s3 C) d+ {+ f( d O( U ●Synopsys, Inc. – PrimeTime VX 8 ~# ~% n( K! E" H5 Q
/ i8 Y1 e; {/ _# |& m ?Design Verification Tools * n1 ~& \" o* j5 } u: }
●EVE – ZeBu-UF4 3 O; @+ b2 }$ R2 j1 O; g5 J% S& b ●Liga Systems – NitroSIM(tm) 3 \5 C. X" z( \. m
●OneSpin Solutions – OneSpin 360 Module Verifier ' b" ?% a( X2 t7 f8 Y4 K5 x7 E3 j; D
Interconnect Technologies and Components & ^0 J6 k) ~; s! ]/ F ●Belden – Belden 1304A/1305A CatSnakeTactical Cat 5e * T& D' @: ] I# T ●Denali Software – DDR PHY Interface (DFI) Standard $ h: {; E( ]" A. o' U! A ●TDK Corporation of America – ESR Controlled MLCCs 2 e3 L) P2 S- S) i, h( |4 x- Y & W- Y" Y! h Q6 j7 h( e9 @5 _PCB Design Tools . b, `, F5 h5 B
●ASSET InterTech – DFT Analyzer 1 N/ M0 v: K _7 J0 |) [6 W% n
●Flomerics Inc. – FloPCB for Allegro 8 r% m9 Z$ v; \5 z5 P
●PCB Libraries, Inc. – IPC-7351A LP Wizard }/ p4 e; Y& P! b* S, U
* V' X& a# _$ S
Semiconductors and ICs 9 e% ~' H+ [! g# { ●Lattice Semiconductor – LatticeECP2M FPGA family ) }0 \6 @- o8 L' F7 r ●National Semiconductor – LM3370 Multi-Channel Integrated Power Management Device ! N8 X0 u+ l% Z7 h% G+ y ~, M ●Rambus – Rambus' FlexPhase ( O$ \/ k% \7 S
( D9 a4 S( U9 @2 Q% ISemiconductors and ICs (IP) 0 @" L" m2 L! a7 }) E7 [# V( i# L ●Stratosphere Solutions, Inc. – StratoPro ( [3 w, h, U/ c' H% a4 g3 O* m
●Sun Microsystems – OpenSPARC T1/UltraSPARC T1 8 ^) D+ Y' Y1 K
●Structured/Platform ASIC, FPGA, and PLD Design Tools % \+ P7 e" K c K ●Altium Limited – Altium Designer 6 3 V7 s: I# ?0 @+ B, t- Z: t ●CoWare, Inc. – CoWare Virtual Platform Product Family ; w* R: l+ a1 M @
●Xilinx – PlanAhead Design and Analysis Tool (Version 8.2) % v& e* x+ p& V G& o' s8 Q
8 |& T( F9 G9 X% ^( \
System-Level Design Tools 2 q! u! d( \# N/ z5 w) X5 z ●Bluespec, Inc. – ESL Synthesis Extensions for SystemC ; `! z" j& i, j( w" X/ ~, e
●Synplicity, Inc. – Open IP Encryption Methodology & X. g4 ?5 f4 V4 l1 U ●Chip Estimate – InCyte Enterprise ! {4 ]$ ^% A. `9 w' C) y8 S 4 _2 O; |) i! L2 JTest and Measurement Equipment ) [% s& d5 o) V; j' @0 A ●Agilent Technologies – J-BERT with industry first built-in clock data recovery (CDR) 3 C9 O% C: O) @: r; k: q ●LeCroy – SDA 18000 ^! N8 A4 e( s( L, C ●Probing Solutions – PSI 2020HV ( g0 u& }1 [/ l* L. ?' I ●Tektronix, Inc. – RSA6100A Real-Time Spectrum Analyzer " t! [& N# e% x( m) k8 f ●Wavecrest – SIA-4000 Signal Integrity Analysis Solution 作者: chip123 時間: 2007-3-1 06:23 PM 標題: IEC DesignVision大獎揭曉 國際工程論壇已在DesignCon會議中，頒發2007年DesignVision大獎。此獎項是頒發給在技術、應用、產品及服務等各方面評選為最具特色，且能為該產業帶來最大利益的各項產品。所有入圍名單，都是由DesignCon技術計畫委員會選出的評審員，從眾多擁有多項得獎紀錄的競爭產品中挑選出來，再從中選出具有創新貢獻及證明對社會有重大影響的新產品，成為2007年DesignVision大獎的得獎產品。 : p1 a, v# o5 d) e" V: }7 A0 y# S; P7 b1 A: G. _" }6 T) n8 ? . A% y$ B- n5 V( ?( O/ u
1 A- C1 } s1 V* vIn the nine categories, the 2007 award WINNERS include the following companies and products respectively: 7 L( y( c7 O' y http://www.designcon.com/2007/exhibition/designvision_2.html * m8 M* d7 z# U: G1 S( M$ f( |9 u
ASIC and IC Design Tools: i2 T1 I$ g: r5 y. A8 L
Cadence Design Systems, Inc. – Cadence Space-Based Router " N. j6 n. E" @" S + y' S/ Y; d, I0 }: B0 u# Z/ h1 wDesign Verification Tools * v6 R, d& ~; O' Z \: kOneSpin Solutions – OneSpin 360 Module Verifier : Q% B, Y. K7 d4 A( B5 N" N ; P6 J% G0 c/ fInterconnect Technologies and Components 5 X9 v* O) g. L/ c3 a3 M
Denali Software – DDR PHY Interface (DFI) Standard ; N! K' X& m! ]& r- [
4 V# e* U3 Y( U3 d4 u+ s
PCB Design Tools % M/ k1 u5 S* Q6 \* X
PCB Libraries, Inc. – IPC-7351A LP Wizard 9 `4 ^# T3 K' e( b4 p
* m/ ~, d6 E1 H: \8 CStructured/Platform ASIC, FPGA, and PLD Design Tools ! Y% } n$ A7 O; |Altium Limited – Altium Designer 6 ! D$ j5 f5 T I# d1 }* r7 x- V# Q4 Z
Xilinx – PlanAhead Design and Analysis Tool (Version 8.2) ( W1 X4 @$ b; g: u0 j) [; n
. V1 q7 N3 E% c3 y
System-Level Design Tools # r8 `" {# q. }2 {7 I2 [ b
Synplicity, Inc. – Open IP Encryption Methodology " _. o) t; V; c0 bChip Estimate – InCyte Enterprise , ^9 d8 M. M. W* T. [
. J+ V w* X& R% p+ R2 v& TTest and Measurement Equipment $ [& O1 P9 {" D" W; RAgilent Technologies – J-BERT with industry first built-in clock data recovery (CDR) - I8 H0 W# n! I! `7 \& dLeCroy – SDA 18000 ! m! l4 q+ V- I8 {& JTektronix, Inc. – RSA6100A Real-Time Spectrum Analyzer作者: masonchung 時間: 2007-4-22 09:55 PM
這些的確是IC Design/EDA界的領導主流4 E6 F% n" L% F
不知有那些人有使用經驗的阿作者: jiming 時間: 2008-2-14 06:20 PM 標題: 2008 DesignVision Award Winners! 一年過去囉！與去年比較起來，差別多大？誰勝誰敗呢？:o1 s- c( B% K2 O* r' D0 D0 q
% r3 H/ V6 E$ ]( `- A Award recipients were selected in eight categories. 6 e9 Y6 s5 q7 [: k+ M; \/ {0 H
: U) ?1 d8 T5 O7 a5 D8 n7 X( x ASIC and IC Design Tools ' I4 E9 Y) {4 r: v) m- ]
Cadence Design Systems, Inc. — Cadence Litho Electrical Analyzer
Design Verification Tools
Mentor Graphics and Cadence Design Systems, Inc. — Open Verification Methodology
Interconnect Technologies and Components
Amphenol TCS — XCede
Semiconductors and ICs
Altera Corporation — Stratix III FPGA
Semiconductors and ICs (IP)
Rambus — The XDRTM Memory Architecture
Structured/Platform ASIC, FPGA, and PLD Design Tools
Lattice Semiconductor — LatticeXP2 FPGA Family
System-Level Design Tools
FuturePlus Systems, Corp. — FS5000 Jitterlyzer
Test and Measurement Equipment
Agilent Technologies — Agilent N6705A DC Power Analyzer
, E5 X- v6 |" T6 f' G( q
Congratulation to the 2008 DesignVision Award Finalists' o" q' M' S& X7 s% [
4 q2 s& Z- `3 b! nWinners will be announced during a special DesignVision ceremony taking place at 12 noon on Tuesday, February 5 in the Theater. DesignVision Awards recognize technologies, applications, products, and services judged to be the most unique and beneficial to the industry. DesignVision Awards also honor corporations and individuals for innovative contributions and developments that have proven important to society. A , U1 k2 j. @' \ ) _4 M; p: V9 [2 h/ }+ f" S ZSIC and IC Design Tools ( o4 X- T! [* i+ V8 |, F
Cadence Design Systems — Cadence Litho Electrical Analyzer
GiDEL — PROCStar II
Sequence Design — PowerTheater-Explorer
Design Verification Tools
EVE — Zebu-XXL
Mentor Graphics and Cadence Design Systems — Open Verification Methodology
Synplicity — TotalRecall Full Visibility Technology
5 F& C, _' l- G) J9 LnXCG時鐘發生器為系統時鐘提供四個可程式選擇的輸出，能夠做好保障，滿足XIO和XDR DRAM裝置的時脈需求。作者: jiming 時間: 2008-2-22 11:44 AM 標題: Altera Stratix III FPGA獲IEC 2008創意設計獎 Altera宣布其Stratix III FPGA榮獲國際電工委員會(IEC)半導體和IC類的創意設計獎(DesignVision Award)。該產品獨特的創新架構獲得IEC青睞，在此架構下，Altera推出性能好而功率消耗低的高階FPGA。獲獎元件的傑出特點在於其DDR3記憶體介面，記憶體速率超過1067Mbit/s。該公司在聖塔克拉拉會議中心舉行的DesignCon 2008頒獎儀式上獲頒這一創意設計獎。 & D$ I. ]3 E' ]# A! J: E ; S6 k' z# z: q* ~( |/ I自2005年，IEC的創意設計獎主要頒發給業界最獨特、最有效益的技術、應用、產品和服務等。創意設計獎提名從創新性、獨創性、市場影響、用戶受益情況及給社會帶來的價值作為審核標準。 R0 w( f6 `2 ]- _0 h% r
' J# ~0 l9 M. a5 J. g7 p3 _/ uAltera Stratix III FPGA最關鍵的架構創新之處在於其低功率消耗特性，包括可選內部核心電壓和可編程功率消耗技術。利用上述創新技術，和前一代高階FPGA相比，Altera元件的整體功率消耗降低50%。該產品具備性能好、功率消耗低的I/O及優異的訊號完整性。創新技術使Stratix III FPGA的DDR3記憶體介面速率超過1067Mbit/s，和競爭FPGA解決方案相比，記憶體性能高出33%。作者: jiming 時間: 2009-3-31 08:14 AM 標題: Cadence ChipEstimate.com IP Ecosystem Wins 2009 DesignVision Award SANTA CLARA, Calif., 04 Feb 2009 " i9 X! Q4 @; n 9 b- ]/ D$ w X, k! VCadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that the ChipEstimate.com IP ecosystem has been recognized with a DesignVision Award by the International Engineering Consortium (IEC). DesignVision Awards recognize technologies, applications, products, and solutions judged to be the most unique and beneficial to the semiconductor industry. ' V, J. e9 t/ I+ M: n
' r2 x) O4 A$ C5 S9 L5 V, ~
"We are honored to receive this recognition of the value the ChipEstimate.com portal brings to the electronics industry," said Adam Traidman, group marketing director, Chip Planning Solutions Organization at Cadence. "The honor is shared with the over 200 IP suppliers and foundries who work together to accelerate our mutual customers' design success." : V& {& ^2 n3 z
, s$ h* r) o% n% \% C* e! M"The IEC's DesignVision Awards recognize top contributions to the design engineering industry. We're pleased to recognize Cadence Design Systems as a DesignVision Awards Winner for its ChipEstimate.com IP ecosystem," commented IEC Executive President Roger Plummer. 1 t ]$ K% I4 W# |4 w5 }, v
$ e! R; q; n5 C9 l9 ?9 N/ JThe ChipEstimate.com chip planning portal is an ecosystem comprised of over 200 of the world's largest IP suppliers and foundries. These companies all share in the common vision of helping the worldwide electronics design community achieve greater profitability and success. To date, a diverse global audience of over 20,000 users has joined the ChipEstimate.com community and has collectively performed over 80,000 chip estimations. ChipEstimate.com is a property of Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation.作者: globe0968 時間: 2011-1-27 04:36 PM
DesignVision Awards 4 D1 ~! x& Z) m: E' H3 v6 S+ Q/ T# Q
6 W2 ?% ^; M* e+ K4 X We will announce the winners live on the show floor ChipHead Theater on Tuesday, February 1st at 4:45pm!Click Here for the official RULES AND REGULATIONS for the 2011 DesignVision Awards..* L# H6 n% o4 j
( _' ~1 E B" Z4 k+ uDeadlines:
Submission Deadline is January 7th.
Finalists announced January 14th.
Winners notified January 21st.
Winners announced live at DesignCon February 1st.
作者: globe0968 時間: 2011-1-27 04:37 PM 標題: DesignVision Awards Finalists ' l3 _) A9 X2 d6 r
' A6 N$ m. k/ }
3M Twin Axial Cable" Q4 y5 Y* ~' s" _4 l
Agilent ENA Option7 k- L: W3 q" r# Z% z
Altera Variable Precision DSP Architecture4 c: F( C$ o6 o" U" h2 ~; _* J( o
Anritsu Test solution# A" \+ G& }2 K: a! R4 @1 |$ R
Cadence Encounter- `: z1 C) h7 P. H* C7 |. f. C
Calibre - K I! f' q2 k4 U x& TChipEstimate.com $ [0 P B4 L4 e2 U( ~. V4 cFCI HPCE 4 h# b( r% H8 p- {8 g$ v% y4 IGaterocket SoftPatch 8 L5 Y* s. h& KInPhi Memory buffer 1 t) ?7 w8 H$ N- X0 z N3 kIR DirectFET 2 ( Y" `- j% u# C$ U& B" y5 MIR iP2010 ; K! z X7 F: A7 U! x" [" @IR IRS2573D+ C! L* X3 U {! {) Y [
Ixia Xcellon Flex 9 k7 f/ {4 z3 Z7 PKilopass Gusto ( J+ G' O o% O& gLeCroy Sparq ) f; V; `0 j D& ?LeCroy Wavemaster8 K$ ~. v( ^3 U7 p/ J+ f- S
Magma Talus 1.2 ; q! r6 X7 _ C* [3 P: y( q) BMagma Talus Vortex- A0 w w5 `! F$ J! U# e
Magma Tekton . f. O6 R( G: HMeritec VPX Plus% [! h# U/ I* _
Molex Impact) O, X& c4 X3 ?+ K" F6 {. K# H- E/ q
Molex Ten60 Power ' m1 y- y$ {# B. {, h2 k/ c: [: K& EQualiSystems TestShell : ], K3 L5 ]/ c7 x. F) oQuartus! t c1 l! ~& N* O' G4 b% M
Simberian Simbeor 2011 ( Z$ g8 q! n8 P2 rSpringsoft Verdi* V8 A" A0 S9 x4 Z
Stratix V3 M2 ?$ t8 E: O% B! ~
Tektronix TLA7SAxx作者: globe0968 時間: 2011-1-27 04:38 PM
DesignVision Award Categories
Category 1: IC Design Tools
Category 2: Design Verification Tools
Category 3: Interconnect Technologies and Components
Category 4: PCB Design Tools and Technologies
Category 5: Semiconductor Components and ICs
Category 6: Semiconductor IP
Category 7: System Modeling and Simulation Equipment
Category 8: Test and Measurement Equipment
8 g& K$ c. H' D( [ We will announce the winners live on the show floor ChipHead Theater on Tuesday, February 1st at 4:45pm!作者: tk02376 時間: 2011-2-15 11:24 AM 標題: Altera 28-nm精度可調DSP模組架構贏得2011設計創意獎 2011年2月15日，台灣——Altera公司（NASDAQM：ALTR）今天宣佈，其精度可調數位訊號處理（DSP）模組架構贏得DesignCon 2011半導體和IC類的設計創意獎。Altera的精度可調DSP模組架構之所以能夠得到設計創意獎的認可，源自其FPGA內建的高精度、高性能數位訊號處理功能，高效的支援了各種精度等級。Altera的28-nm FPGA系列產品實現了這一種獨特的架構，對於DSP演算法的設計人員而言，這將幫助他們提高系統性能，降低功率消耗，減小在架構上的限制。在美國加州聖塔克拉拉會議中心舉行的DesignCon 2011大會期間，Altera出席了這一個慶祝典禮，並領取了2011設計創意獎。 % r8 Q& j" Z( g, L& @' F $ N; N F4 S9 a$ [( F6 ~為滿足業界的高精度訊號處理需求，Altera開發了業界第一款精度可調DSP模組架構。這一種創新的架構支援FPGA中的每一個DSP模組在編譯時被配置為三個9x9、兩個18x18，一個27x27或者18x36乘法器模式，並可以使用多個DSP模組來實現精度更高的模式。這一種架構在每個模組的基礎上，每一個模組都可支援各種精度，每個DSP模組支援從低解析度固點視訊到單精度浮點，直至使用較少外部邏輯的雙精度浮點。如果需要瞭解Altera精度可調DSP模組架構的詳細資訊，閱讀架構相關的白皮書或者觀看網播，請瀏覽www.altera.com/dsp-variable-precision。) F* m! _% R. }" T7 U& x
h6 K/ B, u; Q
設計創意獎開始自2005年，主要頒發給最獨特和對業界最有益的技術、應用、產品和服務等。根據創新性、獨創性、市場影響、客戶受益情況，以及社會價值來提名設計創意獎候選名單。 $ Z8 ], v) q2 U( X2 W' K" S/ H J1 @/ Y5 O" Z8 S. ]3 y8 _' n
Altera公司軟體、嵌入式和DSP市場資深總監Chris Balough評論表示：「精度可調DSP模組架構支援FPGA以更高效率的方式，來滿足訊號處理應用的多種需求。我們在28-nm FPGA中實現了精度可調DSP模組架構，它可支援寬頻、高精度應用，在對性能要求不高的應用中，進一步提高了硬體使用的性能價格比。贏得設計創意獎表明了我們的精度可調DSP模組架構對業界的重要性，明確地展示了Altera DSP的領先地位。」
. A% y$ B- n5 V( ?( O/ u
3 v6 S+ Q/ T# Q
' l3 _) A9 X2 d6 r