標題: free DRAM controller~~~ MIG [打印本頁] 作者: tommywgt 時間: 2007-7-24 12:23 PM 標題: free DRAM controller~~~ MIG Software Support . f5 v* g `5 |3 @0 G
- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i. 4 e- C: o ]# v6 k' o& d
3 T6 [# K) p, w: D/ s9 \7 l7 CPlatform Support 4 u0 X# g$ S# S' K2 s
- Microsoft Windows XP (32 bit) , L, ?3 c# r, Y. L( j8 O8 ?6 \' D9 F+ n
Device Support 2 p, [( f3 W6 e2 U* |$ C- n- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported. 1 U7 W8 x4 Y% o3 d8 \- ^ D; Q3 w) G$ b; A' RNew Features / ]! H; Z# e8 K0 [: sGeneral New Features and Changes & d k) g$ D b) E7 C
- Supports "Create New Memory Part" for all the designs. 7 N/ b% X4 H! {( e7 W
- DDR and DDR2 SDRAM designs for Spartan-3A. : ^$ p" b4 D& f+ X7 f* g' B
- DDR SDRAM is supported for Virtex-5. . K% a- \, B: ^- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM. / a. g0 O8 U$ E4 x6 Q; p/ R3 _- MIG now pops up the design notes specific to the generated design. % ~ x& N! e, D" \
- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs. 7 C4 B" K: ^3 u: @, X3 D
- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes. 1 ]7 p6 i5 z; _' S9 s4 l3 P$ x, \- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2. % Z& y* \" o; \. v1 f- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A. & [$ m8 l# {' a- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST". 7 c+ Q' X9 f5 f3 Z- Default setting "DCI for Address and Control " is changed to "unChecked". $ W, D- P% ~! z) b- Frequency slider is changed to editable box in the GUI. * s" l8 I. Y2 k# v6 m/ w% p& [2 N- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names. 9 |% e1 p, b4 B z( u" [7 r
- Removed console window when running MIG through CORE Generator. - x# z1 d7 \: ?7 d9 `
- WASSO table (Set Advanced Options) accepts only numeric characters. * \9 l* f1 g+ k* R# F: L% {- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32. % `& s t; X ?: A' D
- Provided web links for all XAPPs in the docs folder of the designs. ! Q; W9 {7 D g& R$ V! m9 ]
- Provided link to Data Sheet instead of Log Sheet in the output window. 8 C5 x! C2 k# p
- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window. 4 T8 T7 s/ Y `4 i- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank. 8 C1 R! Q! v1 r) R
- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition. ; ` J" D) t# R) C! v8 `4 S , O/ K( L% T! `$ Z, Z& GVirtex-5 New Features and Changes 1 F9 `1 \* p- |/ U0 tDDR2 SDRAM , w6 q+ K$ x0 m+ d: R: s8 h
- New controller with several high-performance features. All the features are described in detail in the Application Notes. ' @0 u, { K' `) e: C5 a- Enhanced data calibration algorithms for higher reliability. + T' z- z# O3 j. P- Bank Management feature is supported. 5 F/ J/ h V6 C# R6 S- Supports VHDL. 1 f8 ?" _5 |( Z/ y# J
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear. " |1 ~9 F* D9 |$ N) o
- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus. + T( m$ e3 P3 T# v/ ^8 r- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions. 0 s$ S* B# O2 X i# R/ c' B4 ? Y5 V* Y
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 0 S; @* g. F, b* @- v, U3 t# @
b. WASSO is applied to all the memory interface signals. 3 R5 P6 m/ _( D2 b' q4 Q( o$ Cc. Signals such as "Error" outputs are not part of the WASSO count. 1 C0 @2 V$ S+ _- t5 P# |& R
( P. w. p. `1 u6 ?& W% R% g* G: mDDR SDRAM " o/ P& k! z& ]( \& Y" I* ^. h9 c- This is a new design for MIG. Supports Verilog and VHDL. 6 R% }0 s5 t/ Z7 w0 f$ f
- Bank Management feature is supported. & P; ~- S' O$ b# z! E- m+ O
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear. ; _/ S5 N4 F& h( q% f; \# k 4 d6 b& e3 c3 }6 ~: N3 AQDRII SRAM / I6 S' [2 r8 u
- Added support for VHDL. * B/ i" a& a% J6 X( g0 o1 J K" P- Added support for 72-bit designs. 8 ?' l, i* i Q! s! F8 t
- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay. 7 X! s# S; G, j, x- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6 ' B9 [ g9 P0 T/ w) A
- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons. : T3 L2 t, r2 z4 m% [- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. * O/ y; G9 u7 a7 z0 ka. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. , v$ H1 S w0 _$ K1 W! d( |( q( M
b. WASSO is applied to the output signals only. ( N: t% d9 v0 n% R
9 Y& K# X* G' Z: |# Q, S% S, E4 yVirtex-4 New Features and Changes ( d# F! L" l' RDDR2 SDRAM Direct Clocking 8 O1 L( F+ V5 y2 l7 N/ I" D
- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design. % A7 a( O3 r# c! H: i% n Y
- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins. % D, Z' ^- \% h- t$ X- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 4 N% [6 x' ?6 Q) W/ Z+ r, m- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options. 0 u7 w2 z2 I" A5 `
- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers. 8 q: e" v+ z, D- C, [! K+ y
- Removed all TIGs in UCF. The reset signal is now registered in every module. / N( d; g7 `2 s, j7 p. _; ?- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 9 _& D. L+ d& F* V. ^
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. - \: I' o& B& X4 [( h+ S- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. y# X/ W6 ~, _2 A2 I# g% B# C
- Replaced `defines with localparams for Verilog. 6 |; d( W6 r$ t, g4 d c6 |- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. ) K; G# N: ~0 C5 ?' y1 s# @
- Several state machines now use "One-Hot Encoding". 5 z2 i5 t' h! b- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. ) q6 O1 Y/ ?7 Y: o# e. [$ T- Signal INIT_DONE is brought to top module. * p; |3 e0 _3 _, K- Removed the UniSim primitive components declaration from VHDL modules. : s3 @$ ~# H% P9 l- We now support all multiples of 8-bit data widths even for x16 memory devices. ! t+ k k- y4 V6 n; C6 x. b- We support memory devices of speed grades -3 and -667. I3 m: _$ G/ @+ I- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. + X/ I3 h8 v/ {) s. H6 K
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. ( Q( }$ ^: e% r( G( sb. WASSO is applied to all the memory interface signals. ! m g" m( S# ~; g
c. Signals such as "Error" outputs are not part of the WASSO count. 8 p' W. ~" j/ D' y# e( a
& R( L7 R1 N5 a% f. z- q" ^
DDR2 SDRAM SERDES Clocking 1 q( d5 B4 G+ G, d4 _5 O% `
- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note. 2 P# p4 E0 t3 k0 i% e p$ [$ d
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. ) N% }$ p2 e4 k/ Y5 ^
- Support for ODT. # ?3 c( p1 b! |9 a2 Z" s% m$ W! V! c% D- DQS# Enable is selectable from GUI through Mode registers. 7 e' S! J3 D: p4 y- \
- Removed all TIGs in UCF. The reset signal is now registered in every module. ! z) P4 `# M7 h; Y4 i
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 9 |* E8 M6 e6 i4 w
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. & Z2 [/ v# R" g6 z8 F4 {( U
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. / ~( m1 t, n9 V- C% D9 U5 ~6 Y
- Replaced `defines with localparams for Verilog. 3 X- Q) P- ?6 B
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. : X/ ]) b/ y$ G K- Removed the UniSim primitive components declaration from VHDL modules. $ h. [/ Q1 H J0 w" i% h/ g) r) ?
- We now support all multiples of 8-bit data widths even for x16 memory devices. 0 e" i8 M) w/ P+ ]. \/ f* u' ]- D
- Signal INIT_COMPLETE is brought to top module. + B, q3 m" V g6 O- Memory devices of speed grades -5E and -40E are now supported. $ j) m8 A2 e2 z% V9 x( b8 h- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. . c4 \. [/ X5 l4 h5 }3 m, a0 j( t
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. ) V- c; F1 W/ {0 l
b. WASSO is applied to all the memory interface signals. $ {6 H x; _- u- Zc. Signals such as "Error" outputs are not part of the WASSO count. % ]# ^: X5 U2 K5 g7 [( \
- T& ~* T7 Y8 \DDR SDRAM * j' R% z' x# R' Y- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. ! o0 O# D" y' [# G+ U- Removed all TIGs in UCF. The reset signal is now registered in every module. 0 F q2 w1 y9 E, M, ?- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. : C' s; T. I2 i2 d- U- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. $ o' t0 s! [" t# y# H) i
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. # x* s8 k& ]" f8 I- Replaced `defines with localparams for Verilog. ! ~+ l2 @2 A$ `: ]/ B- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. " F: M4 n9 I) z3 c- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. * x# C( M" C( K- X
- Removed the UniSim primitive components declaration from VHDL modules. , K- D7 O- `' x9 F7 G8 a- G6 ~- We now support all multiples of 8-bit data widths even for x16 memory devices. , K/ [8 J9 ?2 y, Y
- The signal "init_done" is now a port in the top module. , x+ k# X0 ], w! q: J5 P
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 7 W" ]8 ?) y0 m" X# x% ?a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 8 O% z: w: ?- ^6 N: Z. t6 F
b. WASSO is applied to all the memory interface signals. 2 M9 ?0 `7 Y. K6 p" ^9 e( Cc. Signals such as "Error" outputs are not part of the WASSO count. 0 E) ?3 X/ C3 b9 o5 Y+ [; v
* v9 J; _2 n1 {/ t sRLDRAM II - N% @ C& U+ b+ u. d8 v. y S5 f8 m
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. , l9 q, E2 ]. F2 v8 `- Removed all TIGs in UCF. The reset signal is now registered in every module. 4 A9 P; [6 W' Y/ ^
- The design now uses CLK0, instead of CLK50 and div16clk. % W: z6 e* g5 D, ~ E: _- CLK200 is changed to differential clocks in mem_interface_top module (Design top). 7 G' G& F1 w8 a f5 l
- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal. ; |0 \0 f: H& b% |. ^% u
- Removed unused parameters from the parameter file. ; ~8 p! Q# ~8 _! Q2 G$ s- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. / W! H5 R. l* O% z# m+ v
- Replaced `defines with localparams for Verilog. 8 G5 a7 N9 p v7 O! M! l5 [- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. , l9 g" d! e8 v" l. @. G- Removed the UniSim primitive components declaration from VHDL modules. , u# _& T3 M0 z: S. N4 p
- The signal "INIT_DONE" is now a port in the top module. $ ~1 F: @* v6 E v- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8. 0 u3 P" {- ~/ U- P! _- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets. ! L% t! D+ s: T5 b- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file. " J/ |; e. W: ] N8 X- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. - s* r8 f7 W+ d- R9 F
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 4 o7 r. y7 D) Z) }b. WASSO count is applied on output signals only for SIO memory types. * F( `0 j* S7 j: d# d4 d
c. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool. % _) c. h% [7 E( e J5 d1 Z; d- G0 w4 \& b1 GQDRII SRAM 1 |5 f% B$ i0 M* f
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. ' M2 R3 p" j! Z( B0 f
- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic. ( x0 t) ^! a9 F7 h% M( M- Supports generation of designs with out DCM. : |% h( ^& T' f* J5 j: D- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC. 4 B+ r% X( r& H; U: H9 g- Removed all TIGs in UCF. The reset signal is now registered in every module. 1 d0 i) T/ C% o8 Z3 E- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. % A" _7 T! X) Y6 A' x
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 2 `9 A/ l6 P7 U4 Q# H0 v
- Replaced `defines with localparams for Verilog. - v7 k! D; P; x5 H: V) e7 s- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. . l0 d8 |' X9 K* F
- Removed the UniSim primitive components declaration from VHDL modules. & c. S' @" y Q& f% T) p$ h
- The signal "DLY_CAL_DONE" is now a port in the top module. . O$ k0 J G6 h( o4 S8 l0 B- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. 8 F# \3 a3 Y. K
- Added support for DDR Byte writes. 8 T3 c, l% ~0 V8 T) T- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. / {! ^" S" g3 w0 j8 w! l% G% w
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. - l }7 [; Z" eb. WASSO is applied to the output signals only. 7 k O1 n1 ~+ i4 G9 \; Ec. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool. - S \3 A% F- U$ m
6 D7 [5 a: Y; t R) ?" I8 V2 ^: NDDRII SRAM ( f7 W! {) V6 L1 Y- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. . h7 P3 E, ?& p3 K- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic. * U% [5 w5 \0 s2 g- Supports generation of designs with out DCM. 5 Y$ @8 y0 L5 I' E& P1 }
- Part CY7C1526V18-250BZC has been removed from Memory Parts list. " U" w, R7 J3 n6 b: j- Removed all TIGs in UCF. The reset signal is now registered in every module. ) t8 ^& \ H8 Y4 @* Q- o- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 4 ^% m4 k- h& X4 y
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. ' [% k; Z6 H8 Y5 Y
- Replaced `defines with localparams for Verilog. ! B/ i0 I! Y# P: }# h- x* F- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. - E1 }, i& i5 \" Q
- Removed the UniSim primitive components declaration from VHDL modules. : b* l' c! }0 R- The signal "DLY_CAL_DONE" is now a port in the top module. % j) D: [' a+ n. l# i& X- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. 3 }6 y- M. ` x" t- Added support for DDR Byte writes. & U# z( h. Z p$ k- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. + z% {/ |* t$ d! ^
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. . O: L Y9 d- i9 w5 x% p# c' K" nb. WASSO is applied to all the memory interface signals. 0 f! {7 F9 H8 @$ G, l
c. Signals such as "Error" outputs are included in WASSO count.作者: tommywgt 時間: 2007-7-24 12:28 PM
太長的東東沒人想看吧! ) Q2 u, _$ Q5 |; e 1 D# n/ }' ~ ^% p總而言之, 這是一個由Xilnx提供的free IP, 用來控制memory用的, 目前都拿來接DDR/DDR2 SDRAM比較多 0 L7 h" f- c2 D3 M. D" a; h O8 ~- X7 ]" s. ~2 L! b+ E8 p6 M
很好用哦作者: steall74220 時間: 2008-5-14 06:08 PM
請問我現在用CORE產生出來的MIG是直接燒在板子上使用嗎??作者: tommywgt 時間: 2008-5-19 12:32 AM
基本上是的 7 F7 V2 P' K# k0 v% M$ Y+ x5 B# {5 w9 T
實際上當然要跟你自己的設計整合一起才會動作者: anita66 時間: 2009-3-17 06:36 PM
沒有載點呀??這是說明文章而已嗎??我想要下free IP呀??作者: qwe11197 時間: 2009-6-21 03:45 PM
剛剛看了一下簡介 - E, S, w3 b' h! m7 P' b感覺蠻好用的軟體 1 V& r: D, `- d5 S5 f: R9 G1 C/ y( y結果沒有載點真可惜 a4 z5 p* ^8 O! C6 m! \1 t自己去搜尋一下好了!!
