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標題: 在鎖相迴路中如何決定迴路頻寬K呢？ [打印本頁]
作者: option318    時間: 2007-8-17 11:35 AM
標題: 在鎖相迴路中如何決定迴路頻寬K呢？
　如題，請問先進們，在鎖相迴路中要如何決定迴路頻寬K呢？它又和Phase margin、Gain margin有關嗎？ :f17
作者: kmchen3089    時間: 2007-8-20 07:14 PM
標題: 回復 #1 option318 的帖子
回復 #1 option318 的帖子
6 p% f1 W0 `/ L2 B: z5 ]- U$ N(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一5 Q# u9 R, }" r
否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump+ F2 l) A7 z: ^+ a6 q
pll ,且亦有unstability issue
6 l/ N1 k2 f2 [9 i1 q- K(see Charge-pump phase lock loops paper by Gardner" c; B! E& Y  H. q( f2 g
IEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)
) Q& B  d3 H5 S7 E(2) loop BW is related to jitter (or phase noise) ,and locking time
# C3 _$ }; m$ y, H7 h+ Rso you have to consider loop BW  from jitter & locking time  spec
8 e5 V! C5 @. M: D1 @(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq) k/ M% ~) F: ?4 x5 S; H$ W
(4) In my opinion ,gain margin is not considered in pll design
作者: jasonxilion    時間: 2007-11-16 09:38 PM
gain margin is not considered in pll design？ : v0 e* V. |! F! q! K
i don't think so.7 a: `$ d7 i1 m. k- [" Z
isn't it dealt with the stability?
作者: 賴永諭    時間: 2008-2-1 07:22 PM
書上都有講哩...加油看看先....
1 ~0 o4 a8 X, {; X* s9 x應該不難找到哩...



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