|
AMD Geode LX 800@0.9W處理器
General Features
+ P! A+ O+ c" F- X! M1 r; O■ Functional blocks include:( m; \3 {- g* N6 e
— CPU Core( e5 [) s1 O3 N+ Q! j
— GeodeLink™ Control Processor
% |' V3 S7 ?# C5 ^% c, `. r/ ^/ K— GeodeLink Interface Units
+ z7 _1 o8 P/ E. O# H/ d* R— GeodeLink Memory Controller0 V2 O5 ?5 ~& X$ K4 R
— Graphics Processor4 `$ m, G m' n& C( @% h! M
— Display Controller
: L% c+ O3 e& t4 f" ~8 N1 a9 P! w— Video Processor$ X) ]( u6 b @ _2 G5 C8 o, A9 `
– TFT Controller/Video Output Port+ ]$ [; u( U, }8 r' Q0 j
— Video Input Port
; q4 o! i% V5 z. T— GeodeLink PCI Bridge% |8 b9 g' L- ], l8 o+ t4 Y
— Security Block
3 ^/ U6 ^% {4 k8 v! ]■ 0.13 micron process
, A0 f! {7 s$ ?1 B■ Packaging:
- D$ M7 b2 U0 {— 481-Terminal BGU (Ball Grid Array Cavity Up) with! S: e P) ^ I7 d2 N
internal heatspreader
) `5 b. Q" Z: k, O8 {. T2 j■ Single packaging option supports all features# H0 z+ |& n- K8 o& i
CPU Processor Features- V- g3 |* M, g O" Q9 H, H# B
■ x86/x87-compatible CPU core9 z- ^, c. t2 x) L% B+ Q+ u# m
■ Performance:! F K# J' C$ Q+ K
— Processor frequency: up to 500 MHz
# Y% t* A9 G3 ~2 U, G* I— Dhrystone 2.1 MIPs: 150 to 450" d) u5 f# ~8 S8 q! h+ E
— Fully pipelined FPU/ t3 C& U8 A% \+ n; C8 j
■ Split I/D cache/TLB (Translation Look-aside Buffer):
2 f7 K) d4 L& x8 N" F$ s— 64 KB I-cache/64 KB D-cache
9 z* [7 D- r+ z$ Y— 128 KB L2 cache configurable as I-cache, D-cache,
{1 n- G2 b4 z& G' {, B& ior both, l5 ]+ y7 l" _5 g
■ Efficient prefetch and branch prediction6 T% ?( q# c. i5 ~3 m+ K
■ Integrated FPU that supports the MMX® and% z5 d/ {8 _0 P( A3 y( N* C
AMD 3DNow!™ instruction sets
( k% P- e4 k$ _( C9 l3 O■ Fully pipelined single precision FPU hardware with$ ~/ ]9 p7 d" g7 X. F) g3 N0 z
microcode support for higher precisions
& q, z! a+ P* y+ Q w( e; mGeodeLink™ Control Processor" }" n Y& v# O2 x3 `
■ JTAG interface:2 }" M9 D( R1 }/ j3 N7 t- y, M( q
— ATPG, Full Scan, BIST on all arrays" t$ G) a a( c, j6 d0 C6 y/ o6 E$ O
— 1149.1 Boundary Scan compliant/ B3 \/ p6 d& }( m
■ ICE (in-circuit emulator) interface
3 `# o) W5 r. f■ Reset and clock control
% g S, d3 M3 b& Z- |$ z- l4 D' @ G @■ Designed for improved software debug methods and
5 t- F+ y( w) g9 O6 j! `( U( A9 @performance analysis
0 t. A! Z+ l/ v8 z8 C6 l" Z■ Power Management:7 C0 L, L0 n/ ]. s
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @* s" m0 m* @; Q
500 MHz max power
- c0 O0 }/ m, N s9 N$ w" s— GeodeLink active hardware power management. Y A' r8 k6 K& _1 I
— Hardware support for standard ACPI software power9 V) g* K7 R1 v# _
management
2 M: H# r6 I2 `5 Y— I/O companion SUSP/SUSPA power controls
* R" l+ ]8 h& R* K! C# J2 |' `— Lower power I/O
B5 J T5 N0 C+ U% {+ L— Wakeup on SMI/INTR8 \& I3 `. @" K# W' `5 [
■ Designed to work in conjunction with the
' h) ~2 |4 }$ \4 ~6 o) i, O5 VAMD Geode™ CS5536 companion device
, L; G4 U; c3 f/ RGeodeLink™ Architecture
|- O! E+ R! ?" ]■ High bandwidth packetized uni-directional bus for) i4 t7 @7 _; M' N. Z, Y2 ]
internal peripherals
: z; v0 F, C* H8 D/ k■ Standardized protocol to allow variants of products to be. ~8 G, k, m" X" \) ]
developed by adding or removing modules
' }- S0 L( b! B■ GeodeLink Control Processor (GLCP) for diagnostics2 C/ k. p. |: C' O% s& g2 q, Z
and scan control! S7 O& |; q2 G$ k( k
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect" h5 R1 U- [$ K! D4 }6 N
GeodeLink™ Memory Controller
7 u2 _ |* n% K9 p: z: J■ Integrated memory controller for low latency to CPU and
5 T# E- j3 c8 n# z$ i! Pon-chip peripherals( w* r% q1 K- J+ o
■ 64-bit wide DDR SDRAM bus operating frequency:; q& Z/ Y+ z$ F# o$ l8 T H* G
— 200 MHz, 400 MT/S7 c3 l8 X" {' x: g/ b2 E9 x) x
■ Supports unbuffered DDR DIMMS using up to 1 GB
3 Q; s* f5 t! yDRAM technology. U% w3 `+ { h7 o- p2 y
■ Supports up to 2 DIMMS (16 devices max)
O; w. j2 y, c& b0 Z) T6 e1 _2D Graphics Processor& ?% j5 j: @+ t6 m9 p
■ High performance 2D graphics controller
( `4 `+ D5 J' L: K■ Alpha BLT9 l* D$ |: O$ f X! n7 r: K
■ Microsoft® Windows® GDI GUI acceleration:
$ _) U* a4 ^8 s2 e' T* u— Hardware support for all Microsoft RDP codes
5 L' c& p7 h, G' G% N; z■ Command buffer interface for asynchronous BLTs
1 m& U8 L9 D+ I, ], o( H■ Second pattern channel support
+ C+ ` ?3 C2 ]1 \( T* G1 U■ Hardware screen rotation |
|