2008年最愛用IC佈局軟體獎

jianping

投票結果僅供參考，請大家保持理性，保持運動家精神

liu.leon

Laker~~~~功能和介面使用上都很方便,比起CadXX好用多了

innoing123

Cadence Virtuoso, Tanner L-Edit, Springsoft Laker, Jedat Alpha-SX
7 t# e! j+ }4 ]  [
1 _2 W+ s( i0 E" e8 D
Expert is a high performance hierarchical layout editor with full editing capability, large capacity and fast layout viewing. Expert can be used in place of Virtuoso, L-Edit, Laker and Alpha-SX and provides the following key features:
- m9 _6 p- ]# d9 T0 J' [

• Expert is integrated with layout verification tools Guardian DRC / LVS and HIPEX for parasitic RC extraction.
• JavaScript for layout automation, parameterized cells (PCells), custom
  $ d9 O5 ~$ y) D! O; L# Eediting commands.
• Expert supports the (OA) OpenAccess database format and interoperable
  process design kits (iPDKs).
• Seamless integration with third-party industry standard layout verification tools (Calibre) allows the user to browse and debug DRC errors.
• DRC Assist warning about potential rule violations before they are created through distance display.
• Hierarchical LVL (layout vs. layout comparison).
• Imports designs from SmartSpice and other spice netlists like
  3 g# X# k: S' W9 Z2 ]$ `HSPICE and SPECTRE, or work with Gateway to perform
  / v+ _6 e, e- ^1 O" Z5 i" P  ]( SDL ) Schematic-Driven-Layout flow.
• Flight Lines guide user on where to wire.
• Node Probing feature traces physical net connectivity through all levels of hierarchy.
• Interactive Short Locator helps to identify short errors to ensure
  * Y8 A2 T+ q3 bLVS-correct layout results.
• Edit-in-Place.
• Cross-Sectional Viewer.
• PDKs are available for leading foundry processes from TSMC, UMC,
  # a8 e+ y, W+ l7 d1 j0 c1 [: [Jazz/TOWER, X-Fab, Austriamicrosystems, MOSIS, AMI and others.

6 f- m+ [' S$ s5 _0 B7 V. h2 |
Cadence Virtuoso, Cadence SPECTRE, Synopsys HSPICE, Mentor Calibre, Tanner L-Edit, Springsoft Laker, and Jedat Alpha-SX are trademarks of their respective owners.

innoing123

See what our customers are saying about Zeni EDA tools.

3 w1 b/ Y# D" ]We looked at Silvaco, Tanner, Mentor, Cadence and Zeni.
- Q" m+ k5 V; W7 g) h9 N
1. Cadence wrote themselves out of the picture with a quote which they claimed was stripped down to bare bones, but Cadence was still 5X what we were willing to spend.
7 V/ H% l! U4 }6 h4 G3 z# P! u2. Mentor prepared a very interesting quote but was still above the amount of money we had. (We are funded through consulting and grants.)
% d$ A4 @- x8 H  g+ f7 K8 |7 b3. Silvaco had a reasonably complete set and we had some interest in the device parameter extraction tool also, but there is always the Ivan issue. (Who's he going to sue today - us?) Also, for the kind of money we were talking about, we would only get full access to the cheap tools, and for the more expensive pieces like the parasitic extraction we would have to rent by the hour.
; I' O! ?) l8 M/ {/ H6 B4. Tanner put together a complete quote including some prefabricated design blocks. However we learned that these had not in fact been silicon tested so we weren't sure how much value they added. The parasitic extraction capabilities seemed extremely limited also - capacitance is only vertical area based, no fringe terms, no wire to wire extraction.

innoing123

I talked to one of their testimonial people, but he had only used the layout tool, none of the rest of the suite. That didn't seem like a whole-hearted endorsement. Another testimonial user said the tools were good for small components but was dubious about whether the tools would scale to a large design. We are aiming at a large chip, so a non-scalable tool didn't seem like a good match.

4 J9 B8 [6 U- E* W% u# c, XFor Zeni, we got a ringing endorsement from a trusted previous user. (I don't want to give his name since I feel like we already imposed by calling him up and chatting with him on a Friday night.) In addition, our own kicking the tires felt pretty good. We read in a large GDS file and it didn't choke. Poking around under the hood showed that the parameterizable cells are all written in TCL and there is a lot of programability.

The Zeni parasitic extractor is quite sophisticated according to the documentation at least - it does field solver accuracy on sample cross sections and then uses pattern matching to extract the parasitics of the entire design. The tool is also Unix based which gave us a higher comfort level in terms of being able to go in and fix whatever we needed with awk, perl etc. Finally, the design kits for the foundry technologies we needed were all ready to go.

innoing123

Overall, we got a sense of solid engineering in the Zeni tool. Whether this is borne out by experience, only time will tell.
We are just installing the Zeni tools as we speak.

+ O$ |8 Y2 ]! e; t/ ]NTU as a world-class University in Singapore has been in the areas of IC Design for years and have all the big EDA companies tools like Mentor, Cadence, Synopsys and Zeni.
But for Zeni, since 2003 we have use it for the full-time IC Design Classes for the undergraduate course for the Degree in EEE. The complete Full-custom IC Design Flow allows students to fully go through a IC Design steps from Circuits Design on paper to Layout and finally to prepare the Design for fabrication.
) L6 }/ Z: [  G4 S3 S$ e" u- dZeni Tool Suites has a very user-friendly interface which allows students to start using the IC tools without much effort. The tool is very much intergrated to provide a full-IC design flow since Z4 and we like it. Overall, the suites provide a strong basic startup tool for IC Design.
  }6 M0 i% g. C4 E" b- ]) DCurrently, we have 125 licenses Full suites of Zeni tools used for the courses and the research programs activites in NTU.
, y7 N1 r. d# X5 T9 t! R-- NTU

Technology

laker 超好用~~又好上手 從Virtuso轉來的