Analog Layout Engineer toghtest job function?

ranica

招聘公司：A famous IC company
& j4 V2 ^8 }8 Z/ {' u招聘岗位：Analog Layout Engineer
! @9 }0 h1 f* ]' b5 b, F' L工作地点：Shanghai
4 D3 g" d  ?" y9 ^7 a$ Z# H
岗位描述：
We expect the engineer to work mainly on analog custom layout design. Help develop CAD capability and automate our design flow.

$ _- n( o! y  N2 b  Y职位要求：
; Z& k: r) F- s7 S$ k  `, o8 G1. Education: a) Graduate from a well recognized university. b) Major in electronic/electrical engineering program is preferred, although other related programs might be acceptable. c) Bachelor degree is a must, master degree is preferred. 2. Work experience: a) Minimum 3 years layout work experience in a well recognized company. b) Experience in CMOS deep sub-micron process, like SMIC 90nm, TSMC 90nm, or bellow. 3. Skill: a) Virtuoso layout tool is preferred; other layout tool skill might be acceptable. b) Familiar with Calibre, or other physical verification tools. c) Good knowledge on CMOS device physics; certain knowledge on circuit theory. d) Unix/Linux. e) Good with Perl and other scripting languages f) Comfortable in communicating in English, both writing and speaking. 4. Other: a) Have the initiative to work on layout. b) Open mind to learning new things.

# L$ |/ G) \: C3 v" I能者與意者請email研發簡歷與chip123聯絡。

mister_liu

招聘公司：A famous IC company
4 k7 X5 o( q1 R招聘岗位：IC Layout Designer
工作地点：Shanghai
  `1 m7 a( E$ z# C9 [0 R
- A. _) D8 y/ ?2 u6 o; @岗位描述Purpose:
The primary objective of this role is to transform IC schematics and related design material into physical IC layout representations.

6 K' I& M. M6 O' @) NResponsibilities:
! J( N0 M/ s, U" J1. Perform challenging IC mask design of advanced analog mixed signal and flash memory IC'S
" d3 l6 V; r- C* u& g2. Develop layout floor plans to optimize die size and circuit performance;
3. Plan and construct circuits, including critical signal and power bussing to analog layout guidelines;
5 F& k5 i) m  X: R+ k4. Perform DRC and LVS verification of layout;
5. Other duties and when required.

* m3 ]9 ?) Y0 }- s; S* l/ o职位要求Requirements:
1. Thorough understanding of IC layout design including use of CAD tools such as DRC, LVS and skill programs
2. Must be good at problem solving
3. Must have the ability to communicate effectively
6 V) p+ y/ N" J% F" z) y% u4. Minimum of 4 years experience in IC layout. Use of cadence Virtuoso XL, Calibre Drc.
4 z7 B1 r8 _) ~1 K& O- F' u
* v1 n% T3 l4 V+ YOther Attributes
( C+ l/ f( Y0 v, NMinimum of 4 years experience in IC layout.
1 g8 r/ Y0 [4 }6 @! Z, K; g, L, JUse of Cadence Virtuoso-XL, P-cells, Calibre DRC/LVS Qualification Bachelor Degree or higher preferred

atitizz

招聘公司：A famous IC company
招聘岗位：ECAD Engineer
工作地点：Shanghai
7 F# i/ g- l0 n, L0 B6 Z9 D
0 r5 f3 B( t: |$ [+ N岗位描述：
% R8 d+ r. X3 n& X2 ISUMMARY Be responsible to use established procedures to design printed circuit boards ESSENTIAL DUTIES AND RESPONSIBILITIES include the following. Other duties may be assigned.  Work with manager and/or project manager to provide information that will aid in the initial quoting process.  Provide Document Control with a complete design package consisting of data and documentation prior to production launch.  Work concurrently with other Design Services departments, Business Unit Management, Manufacturing, Test, Purchasing, and Quality departments through the design phase of a program. Work to provide a design that not only meets the customer’s criteria, but is also of high quality, cost effective, and manufacturable.  Support production discrepancies by incorporating fixes into subsequent revisions in a timely manner.  Communicate and clarify engineering queries from PCB vendor.  Record all ideas, sketches, and pertinent conversations in approved Design Log or Lab Notebook.  Follow appropriate design process, work flow, checklists etc, to ensure quality deliverables.  Stay abreast of the latest technology and techniques to provide designs that are competitive and cost effective.  Exercises judgment within defined procedures and practices to determine appropriate action.  Adhere to all safety and health rules and regulations associated with this position and as directed by supervisor.  Comply and follow all procedures within the company security policy.

atitizz

职位要求：
: i9 A9 b0 a+ J& X  w* KMINIMUM REQUIREMENTS  Bachelor or above  Min. 4 years PCB layout experiences  Experienced on high speed PCB design and design for EMC  Experienced on different PCB fabrication technology  Experienced on different assembly process, know how it impacts the PCB design  Wide range of product design experiences will be a plus  Expert in cadence Allegro design tool, Min. 3 years Allegro design experiences is required LANGUAGE SKILLS Ability to read, analyze, and interpret general business periodicals, professional journals, technical procedures, or governmental regulations. Ability to write reports, business correspondence, and procedure manuals. Ability to effectively present information and respond to questions from groups of managers, clients, customers, and the general public. Fluent written and spoken English required. MATHEMATICAL SKILLS Ability to work with mathematical concepts such as probability and statistical inference, and fundamentals of plane and solid geometry and trigonometry. Ability to apply concepts such as fractions, percentages, ratios, and proportions to practical situations. REASONING ABILITY Ability to define problems, collect data, establish facts, and draw valid conclusions. Ability to interpret an extensive variety of technical instructions in mathematical or diagram form and deal with several abstract and concrete variables. PHYSICAL DEMANDS The physical demands described here are representative of those that must be met by a team member to successfully perform the essential functions of this job. Ability to work effectively under pressure with constantly changing priorities and deadlines. Individual may be required to sit, stand, walk regularly. Be accessible to production floor and office staff and to use required office equipment. Specific vision requirements include reading of written documents and use of computer monitor screen frequently. WORK ENVIRONMENT The work environment characteristics described here are representative of those an employee encounters while performing the essential functions of this job. Individual’s primary workstation is located in the office area, with some time spent each day on the manufacturing floor. The noise level in this environment ranges from low to moderate.

ranica

招聘公司：a top 15 semiconductor company
招聘岗位：IC Layout Engineering Leader
工作地点：Shanghai/Beijing
' D9 X3 L- J, `- m2 ^8 R$ i9 A
职位要求：
Qualifications and Requirements
  X; S5 i; n. l3 b& I8 b: p• BSEE required with more than10 years of experience doing analog layout for mixed-signal designs.
, Z* l# A, y4 I* r6 o7 V* c3 }; O• Strong proficiency in state-of-the-art CAD tools.
• 3-5 years experience in leading/managing team.
1 R. M& l! I0 L1 H• Solid project management experience
. o$ U: v& N9 N$ c9 x& P• Mature personality, good at communication/collaboration with different groups of people.
7 t# d, Q2 |# o! Z+ ~' q• Fluent in English

ranica

岗位描述：
2 U3 S' |7 n& f! C" g( F: d) QJob Description Senior Individual Contributor
% I* m0 h: Z3 ~7 c: k( y) k
2 B, a6 q# [% ?" r8 Q• Lead the analog/mixed-signal IC layout design of complex high-speed & high-precision circuits in various deep sub-micron processes.
( R) T7 C1 w5 S1 \- z: L- |' V& m5 c• Work closely with the manufacturing and CAD organization in the development and debug of process CAD libraries (CADLIBs) for emergent processes.
• Work closely with project leaders and senior design engineers to create & monitor detailed and accurate schedules. Manager / Group Leader
• Lead/manage the layout design team consisting of 10 to 20 layout design engineers with varying levels of experience and expertise in Beijing & Shanghai. Develop the individuals’& the team’s competence to support the overall goals of the China Development Center and corporation
& L/ Z1 l4 q" N• Provide daily coaching to both junior layout and design engineers in the best practices in layout.
• Champion the overall layout design initiatives and provide strategic direction of layout design activities in China Development Center.
3 u+ G  s) E; }% u0 l8 ?9 U, Y* X• Manage layout resources strategically – balancing both project demands and needs for individual development.
• Effectively cross the organizational boundaries to optimize the utilization and development opportunities of the overall layout engineering community. Layout Design Methodology Innovator
• Continually improve the technology and way of working.
• Lead the evaluation and adopt new CAD tools and flows to increase the efficiency (better TTM) and improve the quality of complex, highly-integrated mixed-signal products.
1 e  H% |! _1 y# X1 b( U/ p- E2 q• Establish positive relationship with layout teams out of China Development Center to share best practices and leverage learning
- a6 S" q" \4 b1 |• Closely collaborate with Design Engineers, CAD, and Process Development engineers to improve layout design effectiveness.
• Share the knowledge & arrange training activities to improve the team competencies.

ranica

招聘公司：A famous IC company
9 i& d: }& h1 r- x: n3 L招聘岗位：Layout manager
' g9 k! C0 Q& `% Y5 g工作地点：Shanghai
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( Y: \! R$ K! l岗位描述：
5 @# _/ F3 v4 g% u4 w' K; yDescription 1. 协助电路设计工程师完成高性能混合信号的模拟电路设计和版图设计,主要应用于消费类,医疗和汽车类电子 2. 与跨职能研发团队一起,研发先进的IC产品,最终实现量产

职位要求：
Qualifications 1. 电子工程或相关专业本科学历 2. 5年以上模拟电路设计经验 3. 要求有进行线路图驱动的版图设计经验,以及整体布局规划,芯片级布线,面向制造的设计,设计规则和连接性验证的经验 4. 熟练使用Candence Virtuoso XL者优先 5. 熟悉模拟和数字版图设计工具和流程,熟悉电路设计理论和电路制造工序

ranica

招聘公司：A famous IC company
/ u) z1 O" \6 S, ~% b" J1 t招聘岗位：Analog Circuit Layout Design Engineer
工作地点：Shanghai
, u& ^8 q! `$ s0 J! h) Z
$ U; C. {/ q# q) e5 @1 k& Q岗位描述：
, [- H5 H. \. g% zJob Descriptions: 1. High speed interface circuit layout design 2. Be responsible for the layout design from schematic to GDSII

职位要求：
Job Qualification 1. BS in Electrical engineering or equivalent is required 2. 1 or more years of analog layout design experience 3. Experience with Virtuoso, Laker,... etc and project implementation 4. Proven track records of working independently on layout job from schematic to GDSii 5. Strong physical layout knowledge and parasitic component understanding essential 6. Experience of high speed circuit layout design is preferred 7. Process and device physics knowledge is preferred.