3/20 Mentor Graphics IC-Focus U2U 使用者大會

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Mentor Graphics將於2008年3月20日 (星期四) 於新竹國賓飯店舉辦 IC-Focus U2U 使用者大會，大會將邀請到來自不同領域的六家重量級廠商分享他們的設計經驗，從晶片設計到產出，或是數位/類比及混合訊號電路設計的解決方案，都是此次的探討重點。希望能透過客戶彼此面對面的經驗分享，增加設計技巧，以期將產品的效能發揮到最高效益。

除了當天豐富的議程之外，Mentor Graphics在會場還準備了產品的實機展示，藉由實機操作幫助大家更充分了解Mentor Graphics電子設計工具的強大威力。
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& B; G+ B% {; v& z千萬不要錯過了今年Mentor Graphics台灣區 IC-Focus U2U 使用者大會！
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活動議程及講師介紹

Time Topic 0 S. t/ Q" r9 [, l* D- K) G 09:30-09:40 Welcome Speech 09:40-10:10 Guest Keynote - Dr. Kuo Wu, Deputy Director of Design Service Division, TSMC 10:10-10:40 Keynote - Daniel Yang, PacRim Managing Director, Mentor Graphics 10:40-10:50 Break 10:50-11:25 + z# j0 z4 H  l0 L: b- I Improve Your Productivity with Calibre TVF 議程說明 In the nano-era, physical verification becomes much more challenge. Not only because the number of design rules explodes dramatically, there are also a lot of new problems we need to handle such as the manufacturability issues. Mentor provides Calibre TVF (Tcl Verification Format) for use in coding Calibre rule files. It could help you to reduce the effort of rule file creation and maintenance, and also help you easily customize your rule checks. In this paper, we would like to share some of our experiences of Calibre TVF. Let’s enjoy TVF, now. 5 G$ W0 q5 b7 E/ |. e8 \3 ~Close 3 P. E; h3 g2 X* n 11:25-12:00 Dramatically reducing DRC run time by using Incremental DRC 議程說明 4 a# p& C4 R/ r. C( O8 }In nanometer technology, thousands of design rules will be checked and more and more iterations will be requested before signoff our design. The DRC run time could be dramatically increased from couple of hours to couple of days. Think about this, if you can real time get the DRC results and then correct those errors with the instruction of Calibre DRC to avoid creating new errors before the whole design DRC finished, waiting will not be the only thing you can do. Calibre incremental DRC inclues complete flow, design delta flow and previous result flow to provide more convenient and easier GUI to achieve the reduction of DRC run time in different purposes. We would like to introduce the concept of Calibre incremental DRC and share some sucessful experiences in ruducing our DRC run time by using Calibre incremental DRC and also some suggestions that need to be improved. ; S" g) F5 B+ k0 V3 j  B5 h1 M6 S& _Close # R! r, R2 B. Y1 A& R 12:00-13:30 Lunch 13:30-14:05 Macro Model vs. Calibre xRC 議程說明 - |: \" Y9 _! G3 R, V; ^5 o2 m 1. Macro Model in VIS 2. Why to use Macro Model 2 P: R7 \" O8 v- A/ k3. Calibre xRC & post-simulation 4. Customers' concerns in Macro Model 5. Conclusion + M, l9 V$ z3 N8 S# k6 p0 KClose 14:05-14:40 Review of post OPC checking; Why do we need post OPC check? 議程說明 8 {2 g7 z* s3 w4 J5 r/ \ Coming soon!   ^! N% p* c' a5 T8 H, RClose 14:40-15:15 Application and Yield Estimation - Using Calibre Yield Analyzer for Critical Area Analysis in Layout 議程說明 Application and Yield Estimation - Using Calibre YieldAnalyzer for Critical Area Analysis in Layout Critical Area Analysis estimates random defect impact on a design, which becomes more sophisticated compared to other DFM fields in these days. 8 T# V9 H8 \( i& |. b6 ROn the other hand, to have a methodology which can estimate design quality in manufacturing aspect becomes a strong demand from fabless IC design houses. This presentation introduce UMC's experience for Mentor Calibre YieldAnalyzer CAA. We are glad to share with everyone and exchange ideas and thoughts by this opportunity. And we are going to present a practical CAA system and share the experience regarding how we build up the system. It includes fab data calibration, model selection, cell-level CAA, and service flow setup. With comprehensive index generated by the system, IC design houses can assess the random defect impact on a product, proceeding neceesary enhancement or forecast. Close ) n6 v. g' [% A( L 15:15-15:35 Break 15:35-16:10 ADiT VPI Application on Thermal Sensor 議程說明 2 j" \4 z0 K1 D Coming soon! & ~! o  |, ~5 a% [0 XClose 8 H: Y7 S, s5 g( c5 z' ?. \9 ]0 r) I" K7 y ! J/ w* @9 Q* u5 N+ F( X 16:10-16:45 At-speed Test on a Design with Multi-clock Domain 議程說明 & }* @. m9 v& C3 J$ K- t5 i At-speed test is becoming more and more popular, and handling multiple clock domains and pattern number reduction are two of its challenges. This paper describes a case study of how Mentor Graphics TestKompress was used successfully on a large video chip with 5 different clock domains to test for both transition and stuck-at faults. On-chip modified PLL clock generation circuit and individual clock enabling/disabling scan cell are used to control the multiple clock domains during at-speed testing. In addition, some features of TestKompress like mode definition in the test procedure file and merger flow are shown in this paper, which are used to reduce the pattern number while maintain the test coverage. - E' Q: L7 l6 i' R) zClose 16:45-17:20 Methodology for Improving Scan Diagnosis Resolution of Bridging Defect 議程說明 4 k) g7 N' g8 s3 N" O The goal of this paper is to improve scan diagnosis resolution of bridging defect by finding possible net pairs within a design which are likely to have bridge defect and generating patterns for bridging candidates. The flow mentioned here-in includes net pair identification with Calibre, deterministic bridging ATPG with FastScan and TestKompress, and scan diagnosis with YieldAssist. Test vehicle is a real design in silicon on 90nm technology node, with manual bridging fault injection, the actual fault can be correctly identified with high confidence score. Close 9 O* z1 k: h* x+ w 17:20-18:30 18:30-20:00

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台北/2008年 2月18日 — Mentor Graphics 將於3月20日 (星期四) 假新竹國賓大飯店舉辦IC- Focus U2U 使用者大會，讓來賓有機會能夠與來自不同領域的專家或者其他客戶作寶貴的經驗分享，也讓 Mentor Graphics 的專業技術人員能在第一線了解來自客戶的意見需求。在緊湊知性的研討會後，Mentor Graphic還準備了精采的Magic and Mystery魔幻派對，讓來賓不僅能享受頂級美食，更能有機會親眼目睹魔術的奧妙。

會中將邀請到來自不同領域的六家重量級廠商分享他們的設計經驗，從晶片的設計到產出，或是數位/類比及混合訊號電路設計的解決方案，都是此次的探討重點。希望能透過客戶彼此面對面的經驗分享，增加設計技巧，以期將產品的效能發揮到最高效益。

除了當天豐富的議程之外，Mentor Graphics在會場還準備了產品的實機展示，藉由實機操作幫助大家更充分了解Mentor Graphics電子設計工具的強大威力。

而晚上的「Magic and Mystery 魔幻派對」特別邀請到台灣魔術達人劉謙以及神秘女主持人一同參與，將為現場來賓帶來許多華麗奇幻的表演以及意想不到的魔術秀，保證帶給您震撼性十足的魔幻饗宴！。

, P; C, o# g' K# U7 V2 m本活動完全免費，先進的技術分享、優質的表演、精彩的遊戲、還有頂級的美食。有這麼多好吃好玩還有好康的可以拿，你還在等什麼，趕快報名參加Mentor Graphics IC-Focus U2U 使用者大會!
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晚會入場卷憑研討會問卷換取，現場座位有限，歡迎業界菁英共襄盛舉。
活動相關細節，請參考：http://mentor.u2u.com.tw/default.html

chip123

台北/2008年3月26日 —由全球領先的EDA電子自動化廠商Mentor Graphics 明導國際所舉辦的IC – Focus U2U 使用者大會已於3月20日圓滿閉幕。此次盛會總共吸引了近300名來自全台灣各地的客戶及工程師前來參加。無論是白天的研討會或是晚間的晚會，客戶的參與都極為熱烈。
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& V1 z% T+ s2 g; l3 |/ s大會中邀請到來自不同領域的六家重量級廠商分享他們的設計經驗，不論是從晶片的設計到產出，或是數位/類比及混合訊號電路設計的解決方案，都是此次的探討重點。由於探討題目均是大家工作上接觸的工具，所分享的使用經驗因此特別獲得來賓的共鳴；不止在現場有許多來賓與台上分享客戶有相當密切的對話，會後亦接獲許多進一步詢問的電話，充分反映出工程師們對這個經驗交流平台的肯定與信賴。白天的研討會結束之後，明導國際更精心策劃一場魔幻派對，特別邀請到台灣魔術達人劉謙及美豔女主持人佩甄共同帶來精采的魔術表演，讓長期處在高壓力工作環境下的半導體設計工程師，在繁忙的工作之餘，充分享受了一個輕鬆的夜晚。
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) E0 q$ l# t8 l7 M明導國際亞太區總裁楊正義表示：「明導國際U2U使用者大會的主要目的，是希望能進一步了解客戶需求，並透過客戶彼此使用經驗的分享，讓Mentor Graphics的產品發揮到最高效益。Mentor Graphics不僅僅是將產品銷售給客戶，我們也非常用心提供客戶最好的服務。這次使用者大會的圓滿成功，除了象徵著客戶對我們的強力支持，同時更督促著我們要持續努力，充分滿足客戶的需求。」

. F. T6 Z# d- a. E6 o從活動問卷得知，本次台灣區使用者大會不論在議程的設計、節目的安排、現場的服務都能切合來賓的需要，讓來賓在獲取寶貴知識經驗的同時，還能享受到一流的服務。未來，Mentor Graphics也將不斷地為旗下不同的產品舉辦研討會，期提供業界朋友最新最先進的寶貴資訊。