C-to-RTL compiler touts full-chip design

masonchung

By Richard Goering   
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Courtesy of EE Times
(01/08/2007 9:00 H EST)  
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Santa Cruz, Calif. -- Most C-language synthesis offerings implement algorithms or data path blocks, but startup CebaTech Inc. is taking a different approach. The company this week will roll out the C2R Compiler, a C-to-RTL compiler that promises to generate full-chip designs.


  f* y# e8 R1 x9 |- @' ]1 MThe C2R Compiler generates synthesizable Verilog RTL code from untimed ANSI C code, and also allows functional verification in a native C environment. To that end, a subsequent version of the compiler will also produce cycle-accurate C code. But there is some work involved--the compiler requires a designer to define an architecture by "structuring" the ANSI C code.
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CebaTech (Eatontown, N.J.) intends to provide both EDA tools and silicon intellectual property, and is using the C2R Compiler to design its own IP. CebaTech is currently designing a 1-Gbit/10-Gbit TCP/ IP transport offload engine, intended for introduction early this year.
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$ A, p! H+ X1 [Sherry Hess, CebaTech's vice president of business development, said the C2R Compiler has been deployed at three beta customer sites and is ready for production shipment now. There are no tapeouts yet.

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6 l+ q9 W5 r/ N  o"The sweet spot for the compiler leans to very large system design," said Chad Spackman, CebaTech's co-founder and chief technology officer. He said the company is targeting architects and software developers in such areas as networking, image processing and wireless telecommunications. But that doesn't mean that hardware design expertise isn't needed, he said.
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) T. M  X# B  v) w1 B0 _"Through experience, we have proven to ourselves that it's very necessary to have a hardware-aware person help direct the architecture," Spackman said.
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Spackman believes, however, that the C2R Compiler can completely replace RTL coding, and that's the approach CebaTech is taking with its own IP. "The design we're doing in-house is full-chip, and there won't be any hand-coded RTL," he said. Further, he said, the C2R Compiler can ultimately replace RTL simulation by offering verification in a native C environment. :ar0140


One claimed advantage of using the C2R Compiler is much faster design entry. The compiler can be five to 10 times faster than hand-coded RTL, Spackman said. But the real win may be in verification where, as CebaTech claims, C-language execution can be 1,000 to 100,000 times faster than RTL simulation.

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As always, there's a trade-off in the transition from hand-coding to automation. "We're seeing about a 10 to 15 percent area hit, but that can be very easily controlled by the designer," Spackman said.
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+ q9 ~6 x$ Q: @! P3 \$ B7 O; OStarting with a release in the second quarter, the compiler will generate cycle-accurate C code alongside the Verilog RTL. The compiler is available now for ASIC and FPGA designs, starting at $145,000.

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http://www.dspdesignline.com/products/196801900
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[ 本帖最後由 masonchung 於 2007-2-13 05:55 PM 編輯 ]

masonchung

各位大大不知對此種tool 有何看法？

4 H% N3 V& V0 [# }/ c0 O$ D是否將來的RTL coding engineer 都得改變策略,開始想系統架構和演算法了呢?

henrylai

大概兩年前就聽過類似的概念
大都是高階語言會取代HDL Design
" v/ t2 f  x. u" ?% ]9 t# R2 Y但是到現在 看到走的方向也是如此 不過不是高階語言--> ASIC
; |) P; {) o4 I$ z) C- N- n/ r而是利用高性能CPU加上C 取代一些原本是硬體做的事
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未來這種情況應該會越來越明顯
' V, K7 a; u* V. k+ ~# L8 ]在國外RD team的 軟體工程師人數的增加也是一個佐證

masonchung

所以ASIC工程師都要開始學 Porting 程式了嘛
6 @9 \) Y. y, ]& S4 y$ _henrylai 大大 對哪種高性能CPU比較熟嗎?