11/28 清華大學 Dependable VLSI Systems專題講座

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NPIE本次榮幸邀請到東京大學Prof. Masahiro Fujita分享日本研究團隊於Dependable VLSI System領域之技術研究成果，同時探討智慧電子產業趨勢，誠摯邀請您踴躍蒞臨參加。

" z' R3 b6 Y" U! M3 L2 v  n) T+ h活動時間：101年11月28日（星期三）下午3:00 - 5:00
活動地點：國立清華大學 台達館 R105
+ s( Z( [# g7 V! }! H9 a9 L& ]報名方式：請點選本訊息上方﹝活動報名﹞(報名免費)
4 h9 y8 j$ }! A& _1 Y; J! r% a9 }' v  A報名期限：即日起至101年11月27日（星期二）下午5點以前

演講主題(Title):
Achieving Ultra Dependable VLSI through Collaboration of Formal Verification and Architectural Technologies
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主講人(Speaker):
8 F& L# Y- g4 y' {" NProf. Masahiro Fujita VLSI Design and Education Center (VDEC), University of Tokyo
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1 R, B+ R9 Y+ q3 ?) ~6 w演講摘要(Abstract):
3 `& y9 i2 q8 Y. A4 wUnder JST/CREST funding mechanism, there are 11 research groups being funded as “Dependable VLSI Systems”. In the first part of the talk, we briefly review the research activities performed by Prof. Sakai’s group which try to enhance dependability of VLSI systems through collaboration of formal verification and architectural technologies. The research of formal verification includes formal verifiers for C-based designs, pre-/post-silicon verification and debugging with high-level designs descriptions, and formal verification of high performance processor designs. The research of architectural technologies includes timing-fault-tolerant circuit/architecture against random variation, highly dependable, and dependable and high performance many-core architecture. The architectures developed are the target of the formal verification in order to ensure highly dependable systems. In the second part of the talk, we show details of the research in formal verification part as well ! industrial evaluation of the formal verifier for C-based design descriptions and the tool development for post-silicon verification and debugging.