大家日常設計專案中，哪項工作佔比最重？

ritaliu0604

f the Hardware portion, indicate the percentage of total project effort spent on the following

globe0968

FAE Manager
公      司：Worlding leading MEMS Gyro company
工作地点：上海
$ T2 ?3 F% s& k9 s+ t* x
Job Description
This position be responsible for providing best-in-class pre- and post-sales coordination and support to tier-one customers and the international sales and field apps engineering teams to ensure total customer satisfaction.
0 j% Q9 N2 T. m* S! Z  n. P$ s' n
. Y4 M3 m' x: q3 X+ iResponsibility:
·         Coordinate with sales and FAE teams to communicate directly with customers to manage expectations  and ensure commitments
·         Work with engineering  and product marketing to clarify roadmap and define deliverables to support the customer and sales teams.
( [5 S5 b/ c' i: V5 `( D·         Work closely with technical teams to resolve technical issues.
·         Work with operations to define customer specific supply chain communication and solutions
6 i% ]" L2 f. {. C4 U·         Assist support in defining priority of open customer cases
·         Work to assign necessary and appropriate resources to deliver on customer projects
+ }1 C4 T9 M  {·         Translate customer requirements into specific tasks for all functional areas and proactively capture, track and drive all issues to closure
6 j% K7 W- z$ J- o! ]5 b·         Communicate issue status to customer and all relevant internal teams. Regularly communicate customer status and key issues to management.
+ e! ?  H, F) |( H( c: c% b·         Correctly represent the urgency of issues and escalate issues appropriately

Desired Skills & Experience
( T3 Q, X. A% r0 U  i·         Minimum B.S. (M.S. preferred) in electrical engineering or other related engineering field is required or equivalent work background  and experience
·         5+ years proven history of  System Products (software and hardware) related to Consumer Devices
0 [' D* i6 O. ^2 w2 S( f·         Familiarity with analog and mixed signal devices
* \! }6 ^2 P! T+ D# K·         7+ years'' experience as a Field Application Engineer for a semiconductor company.

ranica

Principal Design Engineer
1 K7 W4 Y" W7 s- C; `公      司：One world top EDA company
8 K  u+ F& Z. ~5 T- Z& c9 i: m$ J工作地点：北京

0 z: K/ u1 R9 u2 L2 v* n/ B: tPosition Description:  
Deliver/implement DDR IP. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.
. {% P/ w2 ~$ w
Specific duties include:
0 Z5 n' r7 a/ C9 W& l- Be responsible for building and leading a high-performance IC design team, owning the IC micro-architecture, package and test platform development, refining the EDA design flow
- Proficiency in logic design, simulation, synthesis, STA and testing
- Proficiency in Verilog and its simulation environment
# D* i0 t& |) h- Good knowledge of IC design
' W1 O# P/ q3 i+ b$ `* |+ r: U
* At least five years experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.

ranica

Sr. Project Manager
& R& d3 r% l3 h+ r/ d公      司：One world top EDA company
4 X8 P% S. q# C& @2 j! O: W' U工作地点：上海

! ]! o4 ^3 F; b/ L7 U7 c: vResponsibilities
2 [' T) ?, j4 F9 {Creates and executes project work plans and revises as appropriate to meet changing needs and requirements.
9 R( A% N: W% R9 L; N% ]Identifies resources needed and assigns individual responsibilities.  
Manages day-to-day operational aspects of a project and scope.  
Reviews deliverables prepared by team before passing to client.  
1 C1 i5 E2 a/ `: L8 e* zEffectively applies our methodology and enforces project standards.  
4 w* D7 _: g* }Prepares for engagement reviews and quality assurance procedures.  
/ l9 K1 N3 ~4 Z2 PMinimizes our exposure and risk on project.  
" [( y! Z# t& ]$ Y# e4 _* DEnsures project documents are complete, current, and stored appropriately.  
Tracks and reports team hours and expenses on a weekly basis.  
; c5 }9 f6 o0 x( B8 s7 [: hManages project budget.  
' A/ b/ X% }0 J: o$ @Determines appropriate revenue recognition, ensures timely and accurate invoicing, and monitors receivables for project.
Follows up with clients, when necessary, regarding unpaid invoices.  
Analyzes project profitability, revenue, margins, bill rates and utilization.

ranica

Requirements:
1 I) w/ ?/ p+ H. ~- B) t; l2 eKey Competencies  
Financial management
Understands basic revenue models, P/L, and cost-to-completion projections and makes decisions accordingly.  
# d" C, n6 d8 |( T2 X7 g, WUnderstands our pricing model and billing procedures.  
Accurately forecasts revenue, profitability, margins, bill rates and utilization.  
5 V3 p9 z! @3 ?: VAssures project legal documents are completed and signed.  

5 U2 O9 w* c: cBusiness Development
Identifies business development and "add-on" sales opportunities as they relate to a specific project.  
Leads proposal efforts including completing project scoping and LOE assessments.  
+ n6 e- X; y; h4 D! F) k6 _Effectively conveys our message in both written and verbal business development discussions.  

Communication
Facilitates team and client meetings effectively.  
Holds regular status meetings with project team.  
1 {2 x2 B( O: I8 p8 \Keeps project team well informed of changes within the organization and general corporate news.  
# T, D; |6 F% K+ H( y& K5 B+ A# ~Effectively communicates relevant project information to superiors.  
* y# z  |: |, j  k' N9 ]' D* f: z$ |9 {Delivers engaging, informative, well-organized presentations.  
; v1 z0 j. o! i# }: |0 w# M' A# [Resolves and/or escalates issues in a timely fashion.  
Understands how to communicate difficult/sensitive information tactfully.  
! Y4 R# n1 \; h/ B+ A0 sTechnical Understanding

; R7 m2 o  g* q3 k; UPossesses general understanding in the areas of DDR and AMS IP designs(USB/PCIe...). Design background is a big plus.
0 j6 k5 ?4 d8 T/ _: c3 L
& U: r) M% p2 K& A" uAt least over 10 years experience in IC industry, required master degree in EE with at least 5 years of qualified project/program management experience. Requires excellent communication skills in English

ritaliu0604

新思科技推出新一代IC Compiler II解決方案 可提升晶片實體設計10倍的效能
+ Y2 O! t6 k; O5 R/ Q! z  S6 S新思科技與業界領導廠商緊密合作  已將此新技術運用於量產製程
1 X4 [* b' @, _! ?& V0 I- E' r
重點摘要:
ž   IC Compiler II可提供10倍速設計規劃(planning)、5倍速實作(implementation)、2倍大容量(capacity)，提升整體設計效能達10倍
ž   此項技術是以全新的延展式架構(scalable infrastructure)、計時器(timer)和分析優化引擎(analytical optimization engines)為基礎
2 n4 k  K5 K0 C' Y9 X! w6 Z- Lž   此解決方案已應用於既有(established)及正在開發的先進技術節點(emerging technology nodes)的生產投片(tapeouts)  

3 R" J8 r% Q5 }. p3 I8 [(台北訊) 全球晶片設計及電子系統軟體暨IP領導廠商新思科技(Synopsys)近日推出IC Compiler II新一代佈局與繞線(place-and-route)解決方案，此解決方案乃目前具業界領導地位之IC Compiler™之創新產品，它是以全新的多執行緒(multi-threaded)架構為基礎，並具備超高容量(ultra-high-capacity)設計規劃(design planning)、獨特的時脈建造(clock-building)技術，和先進的整體分析收斂(global-analytical closure)技術，可協助客戶在進行晶片實體設計時，提升達10倍整體設計效能(physical design throughput)的生產力。同時，IC Compiler II也已成功協助多家晶片領導大廠完成投片(tapeout)。
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新思科技執行副總裁暨設計事業群總經理Antun Domic表示：「從RTL合成(synthesis)、靜態時序(static timing)到實體合成(physical synthesis)等不同的設計階段，新思科技的技術創新促進了整體電子設計技術的演進。而這項IC Compiler II解決方案則是專為提升實體設計(physical design)的速度(speed)所開發，它採用全新的演算法(algorithm)，並提供數據傳輸前所未見的效率，大幅提升實體設計的效能。」

ritaliu0604

在既有(established)及正在開發的先進技術節點(emerging technology nodes)，新思科技的IC Compiler一直是先進高效晶片設計解決方案的首選。從數年前開始，新思科技一方面持續地開發技術，以確保IC Compiler的領導地位，另一方面也著手研發新的佈局繞線系統，來提升設計人員的生產力。這其中的任務包括：開發可支援平行開發(parallel development)的資源及可提升基礎核心演算(core algorithms)的先進技術，以及與廣泛的客戶合作以取得回饋(feedback)，並藉由實際的設計來不斷改善技術。而這項計畫的具體成果，就是IC Compiler II佈局與繞線解決方案。今後新思科技將持續強化和支援IC Compiler，為其客戶提供所需服務，同時也會視客戶的選擇而提供IC Compiler II解決方案。

IC Compiler II是以新的多執行緒架構為中心之全功能(full-featured)佈局繞線系統，能因應超過5億個instances的晶片設計，該解決方案還參照了產業標準的輸入(input)和輸出(output)格式以及常見介面(interfaces)和製程技術檔案(process technology files)，同時引進創新的設計儲存(design storage)功能。此外，從初始的研發開始，IC Compiler II的開發便著重於全晶片層級(full chip-level)，並採用創新的設計規劃能力，來達到10倍速的效能提升，同時將記憶體的耗用減少達5倍。因此，這項解決方案能協助設計人員快速評估眾多晶片設計平面規劃(floor-planning)的選項(alternatives)，以便在適當的時機著手進行晶片實作(implementation)。  
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IC Compiler II解決方案也具備區塊層級(block-level)的各種功能，並且與上述晶片層級功能互補，其背後的支援技術包括新的整體分析優化引擎(global-analytical optimization engine)、全新的時脈產生器(clock generator)以及獨特的繞線後(post-route)優化演算能力，結合這幾項技術可提升面積(area)、時序(power)和功耗(power)的品質(QoR)。此外，IC Compiler II也納入IC Compiler中的技術如conjugate-gradient佈局器(placer)和ZRoute繞線器(router)等。和現有解決方案相比，IC Compiler II平均可達到5倍速的執行時間(runtime)，並減少2倍記憶體空間。執行速度的增加輔以更好的平面規劃，再加上可實現的QoR以及輕量的作業環境(lightweight environment)，IC Compiler II能減少設計iteration的發生，進一步提升設計的生產力。

ranica

DIP Application Engineer
* e, K7 U- D' ]% ^+ b公      司：One world top EDA company
工作地点：上海

Responsibilities:
$ Y$ Y7 D" X) a- q" H8 h1) Providing direct technical support to customers in presale stage to persuade customers to adopt Cadence Design IP solutions for their applications
% _9 W/ Q4 Q8 P$ X7 i. h3 q) o8 y2) Interface with customer architects and Design IP business unit to enable evaluation of application specific IP performance and features per customer’s SOC requirements.
2) Working with the sales team to manage the IP activities in the region to achieve a high customer satisfaction rate and for building strong customer relationships
* C) ?3 K& Z8 W; R& q; ]3) Providing customer feedback on new/existing requirements for Design IP usage from customers to the IP business unit.
: p% ~4 m  g+ ?, b+ Y7 i' M4) Providing direct technical customer support and assistance to enable customers to successfully integrate/use Design IP in their SOC.
5) Writing application notes in situation to facilitate customer usage of the IP

Position Requirements :
1)  Experience in digital/analog design and implementation of controllers/phy
2)  Knowledge of serdes and backend implementation is a plus
3)  Experience with SOC architecture include on-chip fabric (AMBA/Sonics OCP/Arteris NOC), external interconnect protocols (e.g PCIe/Ethernet) and DRAM memory protocols (DDRn, LPDDRn), DRAM PHYs, .NAND Flash (Async, ONFI, Toggle NAND), eMMC/SD, MIPI
" Y% a3 ?' b) s' T5 C& Y4)  Knowing serdes/analog IP is a plus
5)  Exposure to IP-based SOC design flow and real tape-out experience.
3 \! `, Q- K/ s. c$ P3 v- Y6)  Good written and verbal communication skills and problem solving skills are required.
. E2 [; y; h8 _9 r6 p7)  Ability to conduct technical meetings, presentations, seminars and training to customers and to the sales team
8)  Travel within AP region may be required.
9)  Good understanding of the semiconductor IP marketplace and ecosystem is a plus.

mister_liu

DIP Application Engineer
& m  e' {5 d$ g
  k6 \, M' F& m  P4 [, ?公      司：One world top EDA company
4 Q2 M) R: r6 b( O, Z工作地点：上海
9 e+ F( M+ u2 e
; Y( ~4 `* B- h( f9 j! Z& X; VResponsibilities:
1) Providing direct technical support to customers in presale stage to persuade customers to adopt Cadence Design IP solutions for their applications
) ~: d2 F6 y0 i, `2) Interface with customer architects and Design IP business unit to enable evaluation of application specific IP performance and features per customer’s SOC requirements.
2) Working with the sales team to manage the IP activities in the region to achieve a high customer satisfaction rate and for building strong customer relationships
/ M; C" M9 @, r+ z3) Providing customer feedback on new/existing requirements for Design IP usage from customers to the IP business unit.
$ B5 K& J* l) l8 s1 o4) Providing direct technical customer support and assistance to enable customers to successfully integrate/use Design IP in their SOC.
5) Writing application notes in situation to facilitate customer usage of the IP

5 V) t/ _5 `: Y, J* J" VPosition Requirements :
7 N3 B7 ~% C* y/ c- Q( c7 n, i" O8 j6 ^1)  Experience in digital/analog design and implementation of controllers/phy
) P8 w7 m! K6 ?& D2)  Knowledge of serdes and backend implementation is a plus
3)  Experience with SOC architecture include on-chip fabric (AMBA/Sonics OCP/Arteris NOC), external interconnect protocols (e.g PCIe/Ethernet) and DRAM memory protocols (DDRn, LPDDRn), DRAM PHYs, .NAND Flash (Async, ONFI, Toggle NAND), eMMC/SD, MIPI
$ ^5 T1 I7 Q" E4)  Knowing serdes/analog IP is a plus
5)  Exposure to IP-based SOC design flow and real tape-out experience.
6)  Good written and verbal communication skills and problem solving skills are required.
7)  Ability to conduct technical meetings, presentations, seminars and training to customers and to the sales team
, @& q8 h! ~; M- k4 z8)  Travel within AP region may be required.
, A9 r6 c7 m: T) s4 I- P8 G7 H9)  Good understanding of the semiconductor IP marketplace and ecosystem is a plus.

mister_liu

Staff Verification Engineer
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( D4 v2 \3 S; h3 t公      司：one famous IC company
- ?/ f& {. P: P' C+ M: Z工作地点：上海

! ]* W6 F5 x; l2 oQualifications
MS in EE/CS/ME.  
; o0 U1 Q3 c) ?6 NMinimum of five  years experience.
7 |! J7 e5 Q% L7 c/ r8 D8 D/ @Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
" [2 B- }, I; P$ j( E  x$ uCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
Good knowledge ddr protocol and computer system achitecture would be an added advantage.
1 }" L, B6 m, E8 ?Good knowledge of Perl and shell programming would be an added advantage.  
; U) {, {4 z) ~& u1 ~# H8 i
Responsibilities:
-Understanding the expected functionality of designs.
-Developing testing and regression plans.
-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
8 X( q& x+ g' x" a% ]1 [-Code/functional coverage development, analysis and closure.
9 F8 Z+ u% ?5 N
Requirements:
1 d( Y. R- @3 ^4 W- ?7 NExperience & Skill: 5 Years
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
8 p1 E8 C/ q( X0 F8 x3 d-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
-Familiar with C/C++.
2 d7 f, b; k; N! X. I, J-Knowledge of DDR protocol a plus.
/ o, w7 v  o+ o4 z) }( B4 P! E-Independent and self-managing.

ranica

Sr. Reliability Engineer

. S) g& g; S. H. f! \5 `, o7 z7 X公      司：A global PC leading enterprise
工作地点：深圳

Position Description:
       Develop reliability test plan for the company MEMS product based on good understanding of properties critical for sensor performance, material characteristics and limitations, mechanisms of their degradation;
) i, B) N2 f7 u8 _, e       Supervise reliability tests execution, analyze and report test results; facilitate accelerated development timelines;
( }5 z& K5 R, _' l6 B* A& R       Perform failure analysis of the sensor as a whole and its components, materials, coatings to support design and process team in improving sensor performance;
- C/ o8 _2 u* T7 j' t       Job requires ability to plan, and consistently deliver against plan on development and release to production milestones.
0 M$ q* A' O& y( W* p7 \
/ M3 v! Y$ ^( {5 `& WJob responsibilities include:
  M* e; L1 V% T( [! X" _       Work in team environment on developing test hardware and software;  
       Lead reliability characterization of MEMS sensor and its internal components.
: S+ c0 b+ ~% F       Work on failure analysis projects to give feedback to internal process and packaging development teams.
       Deliver against the schedule and communicate status to various levels of management, peers and team members;
       Work in a team environment to determine and improve product and material related issues;
# ?$ W: o, R% i  h% k8 X5 |       Contribute to the design and architecture of future products

ranica

Education:
* F4 g# J0 e8 l6 M. L6 R       MS or PhD in Material Science, Material Engineering, Chemistry, or Physics.

Qualifications:
# ~, q; e" E" A  Q0 U       In depth understanding of properties and chemistry of organic (polymers) and inorganic materials/coatings; excellent knowledge of respective analytical methods, defectoscopy.
  e& D+ D/ J+ W       Experience with semiconductor packaging, flip-chip technology, adhesives, metallic and semiconductor thin films.
       Proven record of successful analytical work related either to introduction of new products in the mass production, or supporting volume manufacturing;
, A' w1 K4 k* u' r3 [2 t1 R/ n       Good knowledge and understanding of JEDEC, ASTM reliability test standards
       Excellent verbal and written language skills (English).
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Experience:
       10+ Years minimum industry experience in conducting reliability tests and failure analysis.
       Demonstrated track record of bringing microelectronic components to volume manufacturing.

ranica

ATE-Sr. Mechanical Engineer
) j. n8 X3 k& q) l' Q; k
公      司：某美资IC设计公司（创业型）
工作地点：深圳

5 R+ e* T4 T" }* ~7 g4 W1 i职位描述
· Responsible for managing the machine shop and the operators / machinist, along with coordinating the work thru the shop and reporting and ordering materials required and used in the machine shop.

" T& v+ Z. m+ s$ G0 X· Hands-on evaluation and interaction with ATE design engineer and CMs in response to test fixture designs on both new and sustaining design concerns.
) m: g0 f8 M/ {! o
' T9 A- j" w# F. ]+ H· Actively troubleshoot test fixture design issues related to test fixture design improvements in  of  thru-put improvements or recommendations.
· Collaborate with and support U.S. based test engineering team  to optimize and complete SolidWorks　Mode　s, assemblies, and drawings.

1 j, `( O/ [8 r) j9 s· Based on quality findings and improvement efforts, provide design suggestions which could improve test fixture thru-put in production and offer potential cost reductions.

5 {4 K2 h& A5 U/ G& a7 o' r· Track and Report and mechanical test fixture schedules and tasks along with assisting in the resolution of any mechanical problem that threatens the test equipment team’s ability to meet production SBU delivery deadlines, including sustaining issues.
2 Z0 n3 N9 z) U9 x, A
· Capable of multiple project assignments and working within a dynamic open office environment is a must.
% I# E0 _3 j! x3 K
· Manage multiple projects, provide estimates, and cost analysis.

# P- I( h7 @" M. q· Coordinate work flow thru the Test Equipment china based CM.

· Proficient user of SolidWorks 3D molding software and experience with SolidCAM, MasterCAM, Delcam for SolidWorks or equivalent package for CNC conversion software, along with mentoring and training of operator.
9 A4 s" B3 ~0 i, \& ?7 b+ f8 q2 q
· Participate in multi-discipline teams utilizing DFMA and DFT

· Provide continual design innovations resulting in improved quality and cost reductions

· Willingness for International travel for the purpose of accelerating the design cycle.
* U2 B2 @( S5 \* ~. q- x
, n7 e1 S  }* P! D9 n· General understanding and basic working knowledge of CNC programming and operation, along with other machine equipment like Mills, Lathe, Surface grinders and other basic tools and equipment used in the machine shop.

. U7 Y# `) e( j4 X· Ability to understand and apply Geometrical Dimensioning and Tolerances to designs.

ranica

职位要求
Must be an outstanding communicator speaking fluently in Mandarin and English, both verbal and written.  
· BSME or related degree with 5 years’ experience in mechanical engineering design.

· Proficiency in SolidWorks (3-5 years’ experience), PDM works, Microsoft office, Oracle.

· Proficiency in SolidCAM or MasterCAM CNC conversion software for CNC machining.
: r& @# h* c1 x% t) A# }& ?
· Ability to identify production/manufacturing problems and lead resolution efforts.
8 r( W/ x- U( r2 Z5 N/ v3 j3 |
1 _3 Y5 i5 |9 D! o" [. g1 F; B  U· Must have a good understanding of different type of plastic and Metals used for test fixture design.
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· Strong self-starter, self-motivated, goal oriented team member.  

· Positive attitude always looking for solutions to problems.
. T+ N0 M8 h! `
· Ability to prioritize work thru a machine shop in order to meet deadlines.

· Capable of multiple project assignments.

/ @# B+ M1 |- [& A# j* f6 ?3 J· Working knowledge of the use of Calipers, Micrometers, Height Gauge and common inspection tools, along with all types of CNC and Mill cutters and tools

mister_liu

IC CAD 工程师

公      司：A famous IC company
1 C; ^( i  T$ E% v工作地点：上海

7 C+ t7 `% q  I: b职位描述
1、IC设计研发团队服务器的搭建与管理，保证服务器的稳定、高效以及数据安全；
2、负责EDA工具及相关license的安装和维护,优化相关环境变量及软件设置，确保设计环境的正常运作，提升自动化程度；
3、为IC设计提供EDA工具技术支持及项目支持，使用perl,shell以及tcl等编写自动化脚本，优化设计流程，提高设计工作效率；
4、协助完善IC设计流程。
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岗位要求：
4 h4 i; P# k, V( i# ]. \1、计算机、自动化及电子相关专业本科以上学历；
2、两年以上相关工作经验；
3、具备撰写Perl/ C-shell/TCL等编程脚本的技巧和能力；
; }$ j+ S9 W7 ]$ d4、熟悉UNIX/LINUX操作系统，熟悉多种EDA工具；
3 S$ {, G+ R1 Z" z5、具有IC设计软件使用经验或了解IC设计流程相关知识者优先考虑；
: P# o  i/ U+ R" e# ?) l; J- E4 x0 q7 @6. 具有良好的沟通能力、分析问题能力、较强的协调能力，以及团队合作意识。