library compiler建DFF cell的疑問

霜淇淋

各位好，小弟打算跑HSPICE改變一下cell library的資料
* G2 [8 K4 c: r/ W- U$ `+ s但有部分還是不太理解，以下是D-Flip Flop(DFF)接腳D及CLK部分
0 X* c' R5 ?7 b( |& v2 W/ u

  pin(D) {
, C( g; N# ]4 y+ y    nextstate_type : data;
    direction : input ;
$ \/ P) h  r0 x7 H% q    capacitance : 0.001165;
    internal_power() {
/ ?; q( v7 l% G7 d1 x" _( A      when : "!CK";
      power(POWER_7x1) {
9 H+ }8 Z1 [* ]- x9 C6 ?" T% v3 L0 U        index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
5 R6 v+ S: }) F1 z, t        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
( |: Z. y# k- ?& p% k    }

values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?

    internal_power() {
, J8 S. s! E' T      when : "CK";
      power(POWER_7x1) {
        index_1("0.009645,0.016106,0.025991,0.046674,0.088957,0.216628,0.447814");
/ L6 j: d: B. h# ^        values("0.000127,0.000122,0.000120,0.000119,0.000117,0.000116,0.000114");
      }
8 M  L2 M' D, `. m2 b: s    }
    timing() {
, a5 u, t% S& i0 R7 L2 Z) m$ z0 m6 l  d      related_pin : "CK";
8 C1 a& t/ O5 m      sdf_edges   : both_edges;
# ]% k* U4 `5 R# F: P8 a      timing_type : setup_rising;
      rise_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("0.029659,0.026470,0.036963",\
% J. D' M% g% Y' t2 x               "0.032032,0.023912,0.031939",\
               "0.004917,0.000010,0.004825");
5 U9 k& n6 w& H. Y      }
% h6 l4 d) C1 G7 F: T9 V! I
values是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?
) P: a6 H4 F* S0 d7 `7 s

      fall_constraint(CONST_3x3) {
5 ?% J: N! p: y. f+ _8 a        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("0.074043,0.058526,0.059156",\
( w) `6 a# i& v+ Q7 l2 D6 h' W               "0.152860,0.139810,0.137970",\
               "0.231770,0.216260,0.216890");
0 i) e$ P* ~* Z0 r, D      }
( A: \9 n) J/ r' M! s- W+ |- }    }

yytseng

internal_power() {
4 u3 `; z/ d6 Y# K+ y* l, ^* O7 o; H      power(POWER_7x1) {
        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
values值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?
8 P$ ^3 r0 V% {$ \& i5 Z===> Wrong !
7 G) J5 ^) p  q& {===> they mean while different input slew (transition) of CK, results different internal power

8 q8 X$ f+ ^  ~; r4 lmin_pulse_width_high : 0.061268;
8 l9 H- {+ `9 o3 Omin_pulse_width_low  : 0.125320;
CLK Hi/Low的長度?
( D# ~5 O! a& p====> No, these mean minimum possible of clock waveform to prevent functional fail, for high (1) and low (0)
% c' k' {) |+ q/ E+ g4 [) \, d
" ~& e; Z8 z  q2 a. |, J) R      index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
9 }2 J6 T8 J+ r7 e) B+ e, O, j      }
    }

values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?
==> No, index1 is often input transition. here represents input slew of D pin

. T% \* X, {$ b. e        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("0.029659,0.026470,0.036963",\
4 j5 M& l7 P8 F/ t* d5 Y# }# O               "0.032032,0.023912,0.031939",\
               "0.004917,0.000010,0.004825");
      }

values是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?

===> yes, but you have to refer index_2 definition in the front of liberty file to make sure.

霜淇淋

timing() {
5 j  O  D7 K! v' _      related_pin : "CK";
! S3 b) t8 d. O1 j' l      sdf_edges   : both_edges;
2 S! K( m' X4 k1 M. ?: n      timing_type : hold_rising;
1 b$ n; w" j% ?9 |; O- [      rise_constraint(CONST_3x3) {
) U8 ?. N/ j$ t0 f. e3 d        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("-0.005932,-0.005209,-0.015703",\
1 S% q/ ]; j4 \8 Z& Q2 m6 Y; p, Q               "0.013887,0.014610,0.004117",\
) l1 ^, C9 i9 w' W* z- z' ^' m               "0.060728,0.056519,0.043560");
' V5 P7 {; D( E6 t( z, A& T! F      }
      fall_constraint(CONST_3x3) {
  E$ r" R. e% z6 z( r% M        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
; Y/ Q/ F! t2 i7 V+ i/ S        values("-0.018261,-0.002744,-0.005839",\
               "-0.028829,-0.021521,-0.028745",\
               "-0.004426,0.053203,-0.004342");
5 D9 R% r0 H- S4 d- S, _      }
2 X8 e3 W9 h0 v% j1 B  [6 o$ {* s* {    }
  }
8 w) ^# M7 ^: }0 m( D  pin(CK) {
    direction : input ;
    capacitance : 0.001915;
7 _+ f7 g: r( w. M  C7 S' @& f" W# u    max_transition : 0.217000;
    clock : true;
5 H. V% @/ a2 X3 S# C4 a- n    internal_power() {
% s4 e3 N2 o0 G, b* ^      power(POWER_7x1) {
        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
      }
    }
, r$ a+ ]* ~/ g( l' N# r: j+ a- V
" @* [& |7 F! E  l0 g
values值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?
6 p  X6 u+ K! _4 v1 a2 t) e6 ]
' l4 T& o( \  b3 A4 q+ ^& L    min_pulse_width_high : 0.061268;
# w( U- `$ C( C    min_pulse_width_low  : 0.125320;

9 u8 J1 V5 B/ @CLK Hi/Low的長度?
% C" @- i# E5 ], H* X! G1 A  }
}

+ I. F6 R& Z, y2 K. r. a+ y) i

( I3 v0 G$ b. i* q: k; C5 Q1 G有觀念誤解的話希望幫忙修正..謝謝

[ 本帖最後由 霜淇淋 於 2009-9-17 02:03 AM 編輯 ]