library compiler建DFF cell的疑問

霜淇淋

各位好，小弟打算跑HSPICE改變一下cell library的資料
但有部分還是不太理解，以下是D-Flip Flop(DFF)接腳D及CLK部分
% g1 F+ M- E, `$ j4 P$ u7 g, O

  pin(D) {
3 h& _7 G' y6 O: j: g6 b' B    nextstate_type : data;
    direction : input ;
1 F2 Y- g0 G- c, j    capacitance : 0.001165;
, l, q* |5 X9 T5 l7 `    internal_power() {
      when : "!CK";
      power(POWER_7x1) {
2 q, A, Y" j; X1 a8 |, g7 s7 j        index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
% C* M+ g9 Y+ F, Z9 E2 U! D      }
    }

% R+ H& [  M; w3 X, T4 yvalues值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?
$ ~, K2 z( g1 v* I. x
    internal_power() {
      when : "CK";
' Y) _3 t: R7 D+ y/ R      power(POWER_7x1) {
) n" Y' ^9 W7 w2 O- k8 ^" y! z        index_1("0.009645,0.016106,0.025991,0.046674,0.088957,0.216628,0.447814");
        values("0.000127,0.000122,0.000120,0.000119,0.000117,0.000116,0.000114");
! Z9 |3 g2 o. |4 D      }
/ O& u& r; N0 M    }
1 H7 q2 I6 `3 V& @8 Y, W    timing() {
      related_pin : "CK";
+ [$ B$ U6 O! |' }      sdf_edges   : both_edges;
+ V8 ?" h; d& }; j1 M( F      timing_type : setup_rising;
      rise_constraint(CONST_3x3) {
: z) }3 \& F' I) F" U9 }* B        index_1("0.006000,0.217000,0.434000");
" o/ m# D2 |: c: w: B7 k3 y        index_2("0.006000,0.108000,0.217000");
        values("0.029659,0.026470,0.036963",\
               "0.032032,0.023912,0.031939",\
! c' f. T# O+ X( L               "0.004917,0.000010,0.004825");
      }

values是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?


      fall_constraint(CONST_3x3) {
: Y) {7 E' [1 ]8 s        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
" y* U8 _% |7 S, v& _        values("0.074043,0.058526,0.059156",\
               "0.152860,0.139810,0.137970",\
. ?8 O  [2 h6 r* D. k. j               "0.231770,0.216260,0.216890");
      }
( |/ L& m3 W4 l2 q' ?! `( U, i! m    }

yytseng

internal_power() {
) L9 B) J- ]6 m  o0 A$ w      power(POWER_7x1) {
: u5 U8 k2 s# [        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
1 ^+ @. P* E2 C8 N* h% R& _* fvalues值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?
===> Wrong !
: T" ?2 |1 x: a===> they mean while different input slew (transition) of CK, results different internal power
6 F( S* B) E- D: J+ z
1 Z& g4 ~" a. F( g5 s. {min_pulse_width_high : 0.061268;
min_pulse_width_low  : 0.125320;
CLK Hi/Low的長度?
5 _% s$ N, z+ |9 f* U====> No, these mean minimum possible of clock waveform to prevent functional fail, for high (1) and low (0)

      index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
6 }% O1 M5 H" g8 R' d    }

values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?
) ^* @  {1 U3 F! K( ~==> No, index1 is often input transition. here represents input slew of D pin

3 p  p1 S, N8 ?+ ~! T3 G' l' U        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
! G& @( Y( v# D        values("0.029659,0.026470,0.036963",\
               "0.032032,0.023912,0.031939",\
               "0.004917,0.000010,0.004825");
      }

& W6 K3 S. v0 s: O" Wvalues是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?
) ?4 |2 i( l2 _5 G* B$ [- i
===> yes, but you have to refer index_2 definition in the front of liberty file to make sure.

霜淇淋

timing() {
      related_pin : "CK";
      sdf_edges   : both_edges;
      timing_type : hold_rising;
0 \* Q3 C! u* i! |      rise_constraint(CONST_3x3) {
6 r& E; h( J4 `        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("-0.005932,-0.005209,-0.015703",\
  A. [8 [0 W" j% I- Y" Y               "0.013887,0.014610,0.004117",\
               "0.060728,0.056519,0.043560");
      }
      fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("-0.018261,-0.002744,-0.005839",\
: i1 y7 r( I4 A' x+ l+ F) P               "-0.028829,-0.021521,-0.028745",\
; ~+ S( q0 Y0 N# A) N( i7 E7 M% E  L               "-0.004426,0.053203,-0.004342");
      }
* ^* r, |2 u) m+ K" B    }
  }
  pin(CK) {
    direction : input ;
) e  p" Z1 B# ]4 e. _    capacitance : 0.001915;
: E: K* e7 B- u9 e" P    max_transition : 0.217000;
    clock : true;
    internal_power() {
# U& F! I+ s1 a* H- X      power(POWER_7x1) {
0 @3 y- C1 P: c" z0 p* v7 ]        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
1 T1 N. p6 U) T% ?2 W6 P1 \      }
) k! _1 U9 P. d' H: s8 W    }


# v; P: ?/ _9 M5 |" ]) X9 A$ qvalues值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?

    min_pulse_width_high : 0.061268;
    min_pulse_width_low  : 0.125320;
" P) }& g" S6 D
3 }/ d+ J& Y, F; FCLK Hi/Low的長度?
% }, a6 G3 r, C) a! O' y- i6 |% I  }
}

( T- \3 G# s) U& `( ^
2 C9 P- n8 k) y+ z# `/ u
' R! L- v3 Y$ b9 w' ]; k  G  ^7 s  X% D有觀念誤解的話希望幫忙修正..謝謝
& P. D" M+ W& ?! r
" q" u: F: A1 k. A[ 本帖最後由 霜淇淋 於 2009-9-17 02:03 AM 編輯 ]