11/30 2011 Apache Technology Forum : Power and Reliability for 28nm IC Designs

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The Apache Technology Forum is a comprehensive one-day technical seminar for chip, package and system designers to learn how Apache's innovative power analysis and optimized solutions enable power-efficient, high-performance, noise-immune ICs and electronic systems. This interactive forum features industry leaders sharing best practices and real design examples of proven methodologies that address critical power and reliability challenges in advanced node designs. Deep technology tracks will focus on practical solutions to meet the power budgeting, power integrity and power induced noise reliability needs of 28nm and 3D-IC designs. For those unfamiliar with Apache, this is a chance to learn what we have to offer. For designers who know Apache, this is an opportunity to stay up to date with our award-winning low-power technology.

Topics Covered
Apache technology vision and roadmap
ANSYS introduction
User presentations on low power, reliability and Chip-Package-System applications
. ?( S4 N/ x  g0 R6 G/ }Technology challenges for power, noise and reliability analysis in CPS

■ 活動時間： 2010年11月30日 星期三 9:00-16:45  
■ 會議場地： 新竹國賓飯店 10樓 宴會廳
■ 洽詢專線： +886-2-8712-8866 分機859 黃先生
/ Q" d7 h4 ^  `* s■ 傳真專線： +886-2-8712-0232
# B+ S6 v# {6 I■ 參加方式： 免費活動 (請攜帶名片1張)
■ 報名方式： 網路、傳真報名

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Agenda
Time	Topic	Presenter
09:00 ~ 09:30	Registration
09:30 ~ 09:35	Welcome	Apache
09:35 ~ 10:20	Message from Apache and ANSYS	Andrew Yang, Apache Chuck Yuan, ANSYS
10:20 ~ 11:05	TSMC Keynote	Dr. Bing Sheu,TSMC
11:05 ~ 11:50	Power Artist RTL Power Estimation Experience Sharing	Steven Chen, Broadcom
11:50 ~ 12:50	Lunch
12:50 ~ 13:20	Apache Product Overview and Update	Dian Yang, Apache
13:20 ~ 13:50	ANSYS Electronics Product Overview	Jack Wu, ANSYS
13:50 ~ 14:35	Coalition of Chip Package Co-simulation to Fortify System Level Power Integrity	Ricky Yong, Mediatek
14:35 ~ 14:55	Break
14:55 ~ 15:40	ASE/Apache JDP – A Novel IC Design Platform for 7 v# Y2 Y' |) c4 Y8 zDynamic Power Noise Validation with IC Package Model 5 Q- f- K9 x( u	Dr. Chen-Chao Wang, ASE
15:40 ~ 16:25	1 i% b% T' X% U- O" P& ]Design Challenges for 28nm and Beyond	Henry Lee, Apache
16:25 ~ 16:45	Wrap-up, Lucky Draw

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