IC設計中前端和後端的區別!?

chip123

IC設計中前端和後端的區別
; X5 M& v- q9 B9 g- Ghttp://www.edacn.net/html/69/78069_itemid_1024.html
2 @3 C5 g9 Y* R$ R: P2006-07-04 17:46:11
6 h  d) _% G+ u
3 R  M) Q! `0 z% v   

  1，前端主要負責邏輯實現，通常是使用verilog/VHDL之類語言，進行行為級的描述。而後端，主要負責將前端的設計變成真正的schematic&layout，流片，量產。打個比喻來說，前端就像是做藍圖的，可以功能性，結構性的東西。而後端則是將藍圖變成真正的高樓。
* H9 _7 d  W" q3 o& c" f% e: N/ t+ [% Z
2 Y) l; {2 H$ _! B      2，前端設計主要是進行功能設計，代碼的編寫，要會使用硬體描述語言，也就是上面有提到的verilog/VHDL等，當然，也會要使用一些仿真軟體。後端設計需要的則會更加多一些了，包括綜合，到P＆R，以及最後的STA，這些工具�candence和synopsys都有一整套系統的。有關心的可以去他們的網站看看。

# _& t. f( }- v. @; [- Z) L       3，其實前端和後端對於編程沒有特別的要求。前端的設計會需要使用硬體描述語言來寫代碼，但是，需要注意的是，這�指的是"描述"，而不像是C或者java之類的強調編程技巧啊什麼的。所以，這個選擇就看你自己了，而與編程沒有什麼特別的關係了。

yhchang

前端的 system simulation (MATLAB)  寫Verilog,
( B2 n% P1 U- b: x: u. R+ \9 ULogic synthesis 與  DFT  比較適合 數位+資工背景且具有系統觀念的人來做
0 J4 I' H2 k6 {( V0 V5 G
2 w1 Z* b/ \/ P& a/ s後端的  APR與  R,L,C extraction  and simulation
APR 也是 資工背景的人做就可以了
但是  RLC 抽取與模擬  就很複雜  做的人 不但要有資工背景
還得懂  電磁學  電子電路 還得了解 積體電路佈局  有一定的難度

yhchang

其實EDA領域最困難的就是 創造出一個全新而且有用的工具
5 @( j0 H. Z6 A更重要的是 要打敗現行市面上所有公司的軟體

ranica

招聘公司：A famous IC company
招聘岗位：ASIC Backend Engineer
工作地点：Shanghai
5 o& }  h& i0 [# q: \" t
岗位描述 Job Description：

* ]! d3 F, F/ E- b1 n2 e: A9 YAs the ASIC Backend Engineer, you will be working closely with the front end ASIC team to synthesize the RTL, clean up the timing, go through the backend flows to deliver the tape-out.

; N# G: @$ |9 ?* p* _职位要求Required Experience：
3 o; I& q. @% l, K
Strong understanding of backend ASIC design flow, ie synthesis, DFT, floor planning, clock
- `2 D# }( e) x7 ?- wtree synthesis, place and route, SI analysis, timing closure, LVS, DRV
Demonstrated knowledge in integrating analog/mixed signal IPs
Hands on experience in low power design and deep sub micron technology
A self-starter that is motivated and a good team player
BSEE required, MSEE preferred
- V) y6 h/ K. n) u3+ years industrial experience

ranica

招聘公司：A famous IC company
招聘岗位：Sr. CAD engineer
( `3 |/ k  q8 Z工作地点：Shanghai
* q6 u  \) J3 s% g3 ^- Q5 U
岗位描述：
( K. n6 T9 v! l6 A( Q! d7 \Duties Develop Cadence based Process Design Kits for state of the art semiconductor process technologies Develop Pcells for Cadence Process Design Kits for Fairchild semiconductor technology architecture development Process Technology and Design Environment CAD system architecture Work with Design Teams to develop and optimize PDK and Design Environment environments
$ i! `" j6 a& ~$ A+ v
职位要求：
Requirements At least 5(five) years experience in PDK Design Kit development Expertise in Cadence PDK Development and tools Expertise in Cadence Pcell development and construction Extensive programing knowledge and experience in Skill, Perl, and other similar automation scripting languages BSEE in Electrical or Computer Engineering

ranica

招聘公司：A famous IC company
4 I1 ?2 |2 n8 x, U! L  N0 r招聘岗位：Backend Leader
; Y9 \( s- \7 l2 i工作地点：Shanghai

岗位描述：
5 I+ c% H* g' i) ]% }4 y" sJob Description:
6 }9 m  P7 L& z3 g- ^" b7 Z1. Lead a team: Build up high performance backend team, participate in the recruitment, setup the objectives, do performance review, support and coach team members
2. Do backend resource allocation, and mediates on short-term priorities
3. Can act as project backend work package leader, manage work package execution from definition to qualification within schedule and quality standard
7 D6 H/ p4 ?" m' O7 c4. Ensure the technical leadership
( P- l' H! O; a. i5. Coordinate backend team’s activity with other teams locally and worldwide
; E( z5 g/ _4 `5 [- X6. Support quality process in Shanghai site

ranica

职位要求：
2 O/ y9 c; f: E3 rRequirements
• B.Sc. degree or above in Semiconductor, Electronics Engineering areas
• 8 year or above experience in backend SoC design with proven SoC tapeout experience
• Have backend team/project management experience
• Strong expertise in Synthesis, floorplan, PnR, SI, LP design, CTS, power analysis in deep sub-macro design.
) C8 V7 i% B0 a+ ~• Strong timing closing and power optimization capabilities.
• Strong experience in synopsys/cadence design tools and flows.
• Excellent analytical, debugging and solving skill
• Experience in data management tools such as DesignSync or Clearcase
+ m/ D: d  H3 Q- P. Z• Experience in Frontend and DFT is plus
( \/ v2 ^- G5 v7 y7 z+ x• Open mind, self-motivated, good communication skills
• Good communication skill, will have frequent communication with foreign teams.
2 K- X+ s3 R+ {7 y( u* u• Good written and spoken English is mandatory

ranica

招聘公司：A famous IC company
  e* S; X$ ?! Z2 s: n招聘岗位：CAD Engineer
工作地点：Beijing

岗位描述：
Duties · Responsible for generating reuse methodology/toolsets to aid in Design/Layout cycletime reduction as well as Design Iteration reduction. · Understand and support an automated CAD environment for the usage of both design and layout community. · Generate automated valid device layouts through coding to reduce layout cycle time. · Able to use the CAD tools to examine technology and design rule suitability for manufacturing and to diagnose problems. · Support the design community with any CAD/software related issues · Support the design community with any Digital/Standard Cell design related issues · Reporting requirements: Weekly and period project status reports. Documentation of methodology and development flows

ranica

职位要求：
Requirements · Strong programming skill is required, minimum of Perl and shell scripting. · Familiarity with semiconductor devices, including MOS, Bipolar, Diode, resistors, capacitors, etc. Knowledge of the operation of these devices in digital or analog applications. · Familiarity with the Linux operating environment. · Familiarity with the Windows operating environment. · Good English communication capabilities.o Familiarity with ESD and latch-up o Ability to translate a raw SPICE netlist to schematic.o M.S., PhD, Electrical Engineering, Microelectronics, or B.S. with experience · Experience in schematic capture through SPICE simulation flow. · Experience in schematic capture to layout generation flow. simulation a plus. · Strong knowledge of problem analysis and diagnostic techniques. · Basic understanding of statistics and design of experiments a plus. · Experience in behavioral and synthesis flows a plus. · Results oriented. · Highly motivated in the pursuit of solutions to challenging technical problems. · Strong communications skills (written, verbal, presentation and listening). · Willingness to work flexible hours, as needed, to allow communications with Design sites. · Able to work independently and be self guided. · Strong interpersonal skills. · Effectively analyzes situations; weighs alternatives – makes a decision – then executes. · Willingness to continue learning new Design Automation techniques by independently reading and studying technical publications. · Able to successfully manage multiple projects at a time.

ranica

招聘公司：A famous IC company
招聘岗位：Physical Design Engineer
工作地点：Shanghai
( L$ P+ u5 }% \, w) Z- \' J
岗位描述：
Responsibilities: 1. Implements IC design with emphasis on backend tasks, including floor-planning, CTS, P&R, power optimization, power/signal integrity. 2. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS). 3. Responsible for Die size estimation, floor-planning, power planning and power analysis. 4. Static Timing analysis (Prime Time) and timing fix. 5.Candidate must be a team player with excellent verbal and written communication skills, strong project management capabilities, and be able to successfully drive a project to completion.

ranica

职位要求：
! O- ^9 v- L% V7 c  T4 ]5 ZRequirements: 1. 4 or more years of hands-on experience in IC physical design, verification and tapeouts. 2. Strong background of deep sub-micron CMOS IC physical design including Floor planning, P&R, CTS, IR Drop Analysis, extraction, timing closure with Signal Integrity. 3. Proven track records of leading tapeouts with at least one use low-power methodology having multi-VDD or switchable voltage-domains. 4. Experience with scripting languages (Perl, TCL, or Shell) to make reusable automatically flow . 5. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler / SOC-Encounter/ Milky-way/ Star-RCX) is a plus. 6. Experience and knowledge about custom layout is a plus. 7. Experience and knowledge about DFT is a plus. 8. Good analytical and debugging skills. 9. Good command of English.

ranica

招聘公司：A famous IC company
& D( S& a4 t( i1 C, V6 l) H8 _; \& b招聘岗位：CAD Manager
工作地点：Shanghai
& B% Q$ R6 }5 g' I: _" ?- T
岗位描述：
We’re a worldwide leader in the design and manufacture of microcontrollers, capacitive touch solutions, advanced logic, mixed-signal, nonvolatile memory and radio frequency (RF) components. Leveraging one of the industry's broadest intellectual property (IP) technology portfolios, be able to provide the electronics industry with complete system solutions focused on industrial, consumer, communications, computing and automotive markets. Responsibilities Manages CAD engineering for design center; Oversees local system and manages CAD tool development team; Develops and supports CAD tools for physical design; Simulation and verification  Working with IT group to administrate design system for hardware and OS, including server,network,workstation,laptop.  Manage whole CAD systems for IC design team, including EDA tools setup, design data management  Develop design flow automation to promote engineers efficiency  Develope necessary scripts or tools to support IC designers.  Arrange to provide training for design team  Working with multi-site employee to smooth the design flow across the world.

ranica

职位要求：

Mandatory Skills  BSEE/MSEE with Minimum four-year related experience  Familiar with UNIX/Linux Windows Operating system,VNC,NX,Exceed  Strong program capability of C, Shell, Perl, Skill, Tcl,etc.  Familiar with Mentor, Synopsys, Cadence or other equivalent tools.  Familiar with Flexlm license setup.  Familiar with process flow and IC design/layout flow  Semiconductor/Device/Circuit background  Familiar with IC verification tools, like Calibre, Dracula, Diva and related rule files.  Tape out support experience is preferred  Familiar with version control tools like DesignSync, CVS,SYN, etc  LSF or SGE experience is a plus  Enterprises network administration experience is a plus  Fluent English speaking, writing and reading, Good communication skills Preferred Skills Strong at problems solving; Teamwork spirit. Education Master degree or higher preferred Experience Minimum of 4 years' experience in R&D center in semiconductor field;

ranica

招聘公司：A famous IC company
招聘岗位：EDA Solutions Architect
( c) Y  [% q- B# C8 H# g4 ?$ g工作地点：Shanghai

岗位描述：
Main Job Function: - Be a key technical expert in pre-sales EDA support for family of XX microprocessors in deep submicron technologies and GHz clock speeds. Guide customers to best utilize high-performance processors cores in SoC designs to optimize performance, power and die cost. - Help define/develop design methodologies for synthesis, static timing, layout, formal verification, design for testability (DFT), JTAG, cross-talk, power-analysis. - Work closely with the sales force and customers. Travel, both domestic and world wide, may be required for up to 30% of time.
, g+ U4 T3 ?! a/ _- I' o
# g( Q8 b  ?: Y! q! u# E% y" d职位要求：
' ], _8 Z( w0 x& W7 e+ w# t5 hKnowledge Requirements: - Experienced with backend ASIC design and integration flow: synthesis, static timing analysis, signal integrity, crosstalk analysis, timing closure, DFT, formal verification, power analysis. - Experienced with common EDA Tools flow, ie: Synopsys/Cadence/Magma - Experienced in tape out flow and physical design verification. - Experienced in 3rd party IP (standard cell, memory compiler) usage. - Strong programming (TCL, Perl, shell script, C) skills. - Strong IT architecture knowledge with setup/configure experience. - Basic understanding of CMOS VLSI IC design and DFT knowledge. - Basic logic/RTL design and microprocessor knowledge. - Basic skills in Linux, PC window setup. - Language: Excellent communication and presentation skills in both English and Chinese. - Experience: Five years experience or more in related area. - Education: BS in EE or CS or Physics (MS or higher preferred). - Other: well organized, self motivated, ability to prioritize and multi-task.

ranica

招聘公司：A fabless IC design company
4 v8 Y4 V2 P3 N$ ^: Y  T招聘岗位：高级数字IC前端设计工程师
工作地点：Beijing
, G% S: `  T& w$ V- i' ^3 H
岗位描述：
主要职责: 1. 确定芯片的解决方案及架构，选择算法，进行优化。 2. 对芯片进行模块划分及Micro Architecture的定义。 3．较大规模ASIC芯片的顶层设计。 4. 独立或带领团队完成芯片设计流程，包括RTL代码编写、验证，综合、时序检查、布局布线。

7 `. s+ ^+ d7 w9 W0 \0 H: i( D8 E职位要求：
职位需求: 1. 具有3年以上IC设计经验，电子或计算机博士／硕士学位。 2. 能够独立设计芯片顶层或主要模块。 3. 有SOC设计经验。 4. 熟悉图像及视频处理技术，数字信号处理，通信协议优先。

ranica

招聘公司：A fabless IC design company
招聘岗位：高级数字IC后端设计工程师
, }  |/ r% R! z' @* `- Q工作地点：Beijing

; M# m4 \7 k# C  s( ]# \岗位描述：
; Y& ~, ~; i( z! IDESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION: Work with global Front-End design team and physical design team for ASIC chip physical implementation. Focus on physical design including block level (full chip) floor planning, timing closure, place&route, physical verification etc.

职位要求：
2 B% |, p8 `- m7 X5 Q) b, J; kJob Requirement: 1. MSEE with 3+ years or Bachelor with 5+ years of industrial experience in ASIC design. 2. Familiar with Back-End (physical design) EDA tools Expertise in place and routing, signal integrity, power analysis, CTS design, DFT, design rule and connectivity verification, timing closure. 3. Knowledgeable in all aspects of deep submicron ASIC design flow .Successfully gone through complete product development cycle. 4. Good analytical and debugging skills. 5. Good listening, writing and speaking English. 6. Good communication skills, strong interpersonal skills and the flexibility. Dedicated, hard working and good team player.

ranica

招聘公司：A famous IC company
招聘岗位：(Senior) IC Design Engineer (IP Front-end)
工作地点：Beijing
岗位描述：
/ n5 F6 ]1 B4 IJob Description: Be part of the design team and responsible for IP Front-end design for the state-of-the-art wireless connectivity SoC products, esp. WLAN IP, single and combo chips Responsibilities: Work with and support SoC architect (team) in high level design, esp. IP micro architecture and IP Interface (SW/HW) feasibility study, high level design documentation, etc. Perform IP/Module design, esp. algorithm to RTL, including design specification, coding, design rule screening, simulation, constraints, formal verification, and detailed documentation. Make design planning and commit to the schedule and quality goal. Work closely with the architecture, algorithm, verification, ME/BE, FPGA and validation teams in solving design and implementation problems. Strictly follow design flow and rules.

8 c8 G9 k6 r; [0 M职位要求：
7 t  {' H/ k: r6 Z! \, dRequirements: Master or higher degree in Electrical Engineering or Computer Engineering. 3+ years experience in ASIC/SoC logic design. Experience in modem or MAC layer IC design is a big plus. Direct experience in WiFi or LTE product R&D is highly preferred. Solid logic design skills and an expert in HDL language. Knowledge in ASIC/SOC architecture and design flow. Experience in DFT, verification or chip level integration is a plus. Hands on in function simulation，synthesis, formal verification and rule check tools. Experience with SystemVerilog/OVM/UVM or STA is a plus. Hands on in Linux/UNIX environment and scripting language. Good English written skill, good oral skill is a must for senior position. Ability to multi-task and work under tight schedule. Teamwork, communication and self-motivated. Ability in quick learning new knowledge and master new skills.

ranica

客户 A famous IC company
地点 Shanxi(Xi an)
3 |6 o1 ?  H) T6 ~: g) a职位描述
Depending on experience, key responsibilities will involve some of the following: Development and optimization of high performance and low power Soc physical implementation methodology Working with European engineers to do block level and full chip floor planning, timing and power analysis, and P&R Design consulting in customer's offices on physical implementation tasks Interfacing with foundry and IP providers on IP imports and test definition Leading engineering teams Additional Academic Responsibilities: Lecturing PD design flow and methodologies to a team of young engineers Compiling course materials with a leading EDA vendor and a leading UK institution/university Giving out PD lectures as well as tutoring the students on assignment and labs Keep up to date on the latest PD EDA tools, process and methodologies Would you like to be involved in some of the most complex chips in China and Europe? Would you like to work with the most advanced 40nm, 28nm and 20nm processes? If so, then this job could be for you. We are only looking for the best engineers; those who are willing to put in the extra effort required to stay ahead of the rest; and those who want to be part of the best physical design team in China. If your ambition is to lead the world in technical excellence, then this could be for you.

ranica

职位要求
+ V- J+ d3 V7 t" v0 z6 c8+ years backend design experience coupled with Bachelor or above degree
* W6 f4 N! x' _2 s3 n* VThe successful applicants will have exposure to some of the following areas:
2 w6 E$ {, `6 z! p0 B" m# DDigital Soc chip design and implementation
Design automation and analysis using scripting languages, particular Tcl and Perl
Design Flows and the EDA tools, in particular tools from Magma, Mentor and Synopsys.
2 ]" H2 `, H+ f7 g! SExperience with tools from Apache and Azuro would be an advantage
Sign-off methodology and EDA tools for STA, Noise, Power, etc.
Structured design styles involving placed gates
( Q' D7 H% S" O7 h2 _4 n/ yATPG tools and methodologies
. M9 q' H  O6 V8 }2 y( gExperience in leading small engineering teams

ranica

资深 IC设计工程师 (架构师或IC实现)
: x* P% A4 u' w# h+ T/ l! |- P& r客户 A global PC leading enterprise
地点 Shenzhen
$ Q" A9 m4 S- M0 |4 N7 `' a) q
职位描述工作内容：
1、参与需求定义，并设计系统整体框架，承担方案的详细设计，代码设计和仿真工作
2、制订开发计划，调配部门资源，保证项目按时保质完成
2 y3 H5 v2 R" \6 ~7 J3、确定验证方案，安排资源完成设计评估

& I, ^$ i0 O7 _职位需求：
1、电子工程、微电子相关专业硕士8+
' Q- M# Y+ X+ g- b+ `2、熟悉IC设计开发流程， 熟悉计算机编程语言，熟练掌握verilog语言。
9 y  k" n$ d2 @3、熟练使用Synopsys公司的IC设计相关EDA软件，特别是综合、静态时序分析、仿真验证
5 W7 k) M' k/ O4、三年以上大规模数字集成电路前端设计经验；至少经历过两个以上完整地芯片开发流程中的设计工作；
5、熟悉ARM体系架构，具备SOC设计实现经验优先
. U! r! ~! u) _/ r9 M, n4 c6、掌握数字电路结构的功能和特性，有较强的理论分析和钻研能力
2 c6 I- g9 m5 u. t& W! l7、有良好的团队精神，较强的沟通能力