身為IC設計者，我面對的最大壓力？

ranica

CAD Engineer [系统编号：79171319589]

公      司：semiconductor company
工作地点：北京
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1 Q3 D. ^: v6 F' G4 g2 [+ J/ hJob Description:
Collaborate with *** CAD teams to develop industry leading design flows and methodologies for analog and mixed-signal designs using nanometer technologies, with emphasis on improvement of layout productivity of analog circuits, including usage of advanced Cadence IC6.1 features, design for manufacturing (DFM), metal fill, physical verification and tapeout flows. Write scripts and utilities to enhance these design flows. Provide CAD support and methodology training to *** design and layout community. Write application notes and document ***’s analog/mixed-signal CAD flows. Work with EDA vendors to drive ***’s interest with regard to analog/mixed-signal tools.
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, F# |: J4 [4 v( U, w: eQualifications:
-         BSEE or above, with 3~5 years relevant industry experience.
7 p; o. F# H/ T8 C1 Z5 ~; m-         Solid understanding of advanced semiconductor process technologies
-         In depth familiarity with layout of analog and mixed signal circuits including knowledge of layout effects (i.e. matching, reliability etc.) and DFM rules for advanced technology nodes
-         Understanding of nanometer design rules and physical verification runsets
4 e* j  @* G: i9 t) F" ~-         Solid knowledge of Cadence DFII
  o7 c( _$ @3 h  m1 R* y-         Knowledge of physical verification tools like Mentor Graphics’ Calibre
-         Knowledge of Skill, perl or other programming languages
8 i1 s9 I* r, i' D6 J% {  A-         Strong written and verbal communication skills

ranica

Principal AMS Physical design engineer
3 N  I) q3 Q! e5 ]公      司：One world top EDA company
工作地点：上海
) R% ?* c/ Q1 r& p0 S' U
职位描述
Skillful capable of physical design of Analog and mixed signal area: Matching sense from transistor, Resistor and capacitor, Power and Ground coupling, Signal path from Differential pairs, etc, if knowledge on digital blocks P&R prefered.
% I2 m  _$ y1 PIn-depth knowledge and hands-on experience on AMS CAD support, such as write Scrips to support PDK(pcell, call back), ams back-end stuffs, including Skill language, Perl, verification runset improvement etc  
Proficient with xx layout tools specifically Virtuoso XL and Assura (xx 6.1 experience a plus)
Experience in 65 nm and below analog CMOS layout, verification (DRC, LVS), and top integrated tapeout to foundry
* B5 C& S( [4 T) ?9 s& x9 lAbility to coordinate with the other analog IC circuit layout,  ensuring robust, efficient, consistent and successful delivery of analog IC circuit layout.
4 @2 B6 N( ~4 tFundamental understanding of IC design technology and process/methodology  
Skilled in Analog IC top level chip assembly including floorplanning and block layout
edicated experience on key macros is prefered: SerDes, High speed/high resolution Data Converters; High Speed PLL''s; Low Noise Design;
# v) d9 V8 S- m) c1 s) |Hands-on experience conducting DRC/LVS analysis and recommending appropriate solutions
Solid understanding of IC design technology and process/methodology in AMS layout

8 X/ `1 o# c. Q- a" C) WPosition Requirements:
7 H7 o8 P, I& O0 F' h BSEE degree with >6+ years of applicable experience in advanced analog and mixed signal design industry. Essential that the individual demonstrates strong communication, verbal and written, and project management skills. Requires very good communication skills in English and Chinese.
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Company Info Type:
; s+ T& G/ d) ?+ a4 p9 e  h. r$ z/ x Global Default
  
Company Information:
6 Q, q& o1 B' }( r6 q xx is the global leader in software, hardware, and silicon IPs that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs and with higher quality.

ranica

Senior/Staff DFT Design Engineer
5 b5 l% A4 B9 ?: s, Y0 p公      司：A famous IC company
$ T2 t% E, z9 F3 ^( n0 j5 A工作地点：上海
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$ G6 m6 [4 Y; o$ `Description:
/ F: t; o5 `- N6 `& g! O- Block, IP and SoC level DFT implementation (bscan, scan, mbist, jtab, analog test structure, etc.)
- work with IP vendor (internal/external) to analyze DFT integation issues
2 M% m$ I/ V( e/ n- DFT STA, constraint generation, formal and timing closure
- DFT flow development and maintenance  
- test vectors generation and verification
( q; a: t: h% s2 c: G2 D( Z0 L4 Z- interface to backend team on physical design and timing closure
- interface to test engineers on ATE and vectors bring-up and debug
) n5 @1 t, ~: I: z+ o) K- chip DFT quality sign-off

Qualifications:
Must have:
- minimum 4+/8+ years of DFT design and integration experience
+ c- r' e. C% n% D1 {- hands on DFT implementation experience (bscan, mbist, scan, IP testablity integration, at-speed  
scan, IDDQ test, ATPG and fault simulation)
& \, J" z7 o- m* e3 L- \+ N6 m- expertise with DFT tools from Synopsy, Mentor, Syntest and Logic Vision
- strong logic design and verification backgroud solid experience in STA
: a* A+ E- M1 @  i) U- proficient in Perl, tcl and shell programming
( z1 J5 j, f. u, I5 B; \* K- BSEE degree or above
- good team work spirit  
3 `; d- `. W1 G, X/ ~
2 W; a% a( D* Y6 RNice to have:
- familiar with DTV/STB architecture, design, and IP  
4 _) ]2 k; j: P) a) Q- proficient in C++ and system verilog

globe0968

Principle SI/PI Engineer
6 A0 B7 S) `/ v公      司：One world top EDA company
% G% e+ Y8 _3 l5 U, v6 e/ x工作地点：上海

Position Description:
Complete power-delivery system analyses across chips, packages and boards. System-level SI analysis, including simultaneous switching noise analysis of high-speed signal transmissions, and advances physical design for single- and multi-chip packages, states-of-the-art 3D packages, and systems in packaged (SiP). The engineer should be able to act as a strong team member and contributor.
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9 a  k" D9 U* _# t+ J6 ySpecific duties include:
0 i4 z, `/ O, t+ \! H+ }! h4 k- Be responsible for building SI/PI/SiP design flow for High-speed IP Design
% P& Y& d0 p4 z. l2 a& m# f& z- Proficiency in Cadence tools: Allegro and Sigrity  
( O, p3 A+ @4 h) G; b1 b& z! G+ I- Proficiency in Hspice or spectre simulation, especially in high-speed simulation.  
* s4 e' F$ u# T- Good knowledge in modeling, for example IBIS.
- Good knowledge in high-speed PCB design.
- At least eight years experience focus on SiP and SI/PI analysis, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment is required.
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Position requirements:
8 w% @( E2 B" C7 bEssential Qualifications:  
1. Must have BS degree with 10+ years of applicable experience, MS degree with 7+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
3 \9 b$ y3 _& U5 ^. e2. Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English.

& h0 w* P  k- pDesirable Qualifications:  
A  minimum of seven years relevant experience in industry.  
& b% K" p. E! Y1 ^0 X- At least five years experience driving SiP/PI/SI project.
- Will have demonstrated successful completion of 10+ projects as an individual contributor

ranica

DIP Application Engineer
- m  W& t$ C4 B) Q5 u7 Q5 l( c公      司：One world top EDA company
) [$ N0 C% ]) q$ v工作地点：上海

' ~+ }1 f8 O% k' K9 K3 G+ w, G' G' PResponsibilities:
, Z" \0 z4 E& `) Y0 _" F1) Providing direct technical support to customers in presale stage to persuade customers to adopt Cadence Design IP solutions for their applications
2) Interface with customer architects and Design IP business unit to enable evaluation of application specific IP performance and features per customer’s SOC requirements.
& ~( u( c* o- o6 Q# t- u2) Working with the sales team to manage the IP activities in the region to achieve a high customer satisfaction rate and for building strong customer relationships
2 v+ @1 F3 }2 s3) Providing customer feedback on new/existing requirements for Design IP usage from customers to the IP business unit.
4) Providing direct technical customer support and assistance to enable customers to successfully integrate/use Design IP in their SOC.
4 N# V; H. J; z* E& M% c7 T8 ]- j3 E5) Writing application notes in situation to facilitate customer usage of the IP

Position Requirements :
4 z( X  h2 b. n1)  Experience in digital/analog design and implementation of controllers/phy
2)  Knowledge of serdes and backend implementation is a plus
3)  Experience with SOC architecture include on-chip fabric (AMBA/Sonics OCP/Arteris NOC), external interconnect protocols (e.g PCIe/Ethernet) and DRAM memory protocols (DDRn, LPDDRn), DRAM PHYs, .NAND Flash (Async, ONFI, Toggle NAND), eMMC/SD, MIPI
4)  Knowing serdes/analog IP is a plus
5)  Exposure to IP-based SOC design flow and real tape-out experience.
9 ^7 F# B4 O, K6)  Good written and verbal communication skills and problem solving skills are required.
7)  Ability to conduct technical meetings, presentations, seminars and training to customers and to the sales team
8)  Travel within AP region may be required.
* r- Y% M. c1 a5 ?7 R9)  Good understanding of the semiconductor IP marketplace and ecosystem is a plus.

ranica

Senior Engineering Manager
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. e( }# @3 X# j' w) Q$ h: N" B公      司：One world top EDA company
8 m& u& l+ v) ^3 g. J工作地点：北京

Position Description  
; a3 z) ^. b; {& y4 R1 s1. World’s leading design companies rely on xx technologies to deliver the latest design innovations in consumer,
) U* d! y" d7 cmobile and enterprise electronics. We are looking for a strong software engineering leader to join our team and contribute to the continued growth and success of the company’s flagship products, including ADE and AMS Designer.
2. In this high-impact career opportunity you will be responsible for delivery of cutting-edge features in mixed-signal simulation and the Virtuoso environment, including technology leadership, team development and people management.
3. You will also work with a cross-functional team in Beijing and North America to ensure that our software is developed, tested, and documented with high quality.

3 T. }( z1 q# p% o' Y. [" A$ X/ h$ _" U/ |Position Requirements  
8 Z# F$ o9 t8 V. g( H0 e2 \- z8 zRequirements:
1. Experience managing software development teams in the EDA or related industry
2. Successful delivery of software products over multiple release cycles
4 M3 C4 S$ {- U/ T& t1 e3. Proficiency with build and version-control systems
* @. t# N0 x$ U/ r1 W" \4. Strong software engineering skills in C/C++ and familiarity with Linux/Unix development
" D8 a5 f) d2 C5. Excellent written and oral English communication skills
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7 u$ f% p$ ]% S. \5 pPreferred skills:
+ q' K2 M* n8 Z2 @5 Y% A& z' a1. Prior experience with analog, digital or mixed-signal simulation using SPICE, Spectre and Verilog languages
% q' }2 q" ^5 t$ e- ?8 |, T+ {2. Exposure to the Virtuoso environment or other electronic design platforms
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Education:
) S! V  M1 s8 `7 [8 xB.S. or higher in engineering, computer science or related field.