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標題: 7/29 Cadence Tech Forum 2010 [打印本頁]
作者: heavy91    時間: 2010-6-28 02:28 PM
標題: 7/29 Cadence Tech Forum 2010
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3 s5 R8 [5 X( t# u$ PCadence益華電腦為電子設計產業提出設計的未來之路!  提供一個從設計開始到系統整合，適合於系統整合、應用開發與系統驗證的完整平台，這就是Cadence所勾勒出的EDA未來之路。EDA360願景能夠讓半導體公司建立威力強大的產品，讓消費性技術供應商能夠運用硬體、軟體與服務結合的生態系統，提供元件平台，能夠幫助公司具備更高競爭力與獲利力。
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8 d, r* @9 A1 g7 `% {9 ]　Cadence Tech Forum 2010讓所有電子產業設計專家能夠會見彼此，與Cadence益華電腦使用者、設計開發工程師， 和各業界專家一同討論，一同激勵電子設計產業的新願景。同時Cadence Tech Forum 2010亦提供了一個機會，了解 Cadence 益華電腦和其他友好夥伴共同開發的解決方案，與如何運用 Cadence益華電腦技術進行創新與研發。
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) L9 r* o9 W  i2 L  U8 y  n5 Q　今年Cadence Tech Forum 2010活動議題涵蓋廣泛，其中包括幾個最令人矚目的話題: 低功耗設計、先進製程下的設計實現、正規驗證、 constraint-driven設計、系統封裝設計和電子系統層級設計等。5 V, m  L% h/ `3 f) h+ r+ t3 i

& C/ b4 P6 K4 b- r, D# Q3 H; u3 V　歡迎參加Cadence Tech Forum 2010，讓你有機會更進一步了解Cadence益華電腦新的解決方法和產品特性，以及未來產品願景與策略。
作者: heavy91    時間: 2010-6-28 02:28 PM
TimeSpeech/
( y# D: _* R# U- m- b1 w& xPlatform		TopicSpeaker
09:00~09:30Registration
09:30~09:40OpeningWelcome Remark

Veronica Watson,# T+ J1 Z5 v( J1 d3 _9 y' E/ b
AP President of Cadence Design System8 e" l+ M# ?' x
Willis Chang, ! O1 O! y) S0 g+ A& n0 q+ _+ @. v
Country Manager of Cadence Taiwan
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09:40~10:10Keynote EDA 360: The Way Forward for Electronic Design

Charlie Huang, # p7 x, e8 M7 N
Senior Vice President and : l. D  |0 F1 C% u* `" H
Chief Strategy Officer

10:10~10:40
& J( d* V) G  K0 }7 y* V7 oKeynote		Cadence open integration platform with integration-optimized IPBrian Gardner,
4 W. {, o4 e8 G& k2 t# JGroup Marketing Director, New Business, Cadence
10:40~11:00Break (Proceed to Breakout Rooms)
Custom Design   ]' B" b, [' k0 [  Z: Y/ X3 g8 q
(Meeting room A&B, 13F)
11:00~11:50CD01TSMC AMS Reference Flow

M. J. Huang,
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11:50~13:30Lunch
13:30~14:20CD02Virtuoso IC Design Platform 6.1.4 - Analog Design Exploration and OptimizationAlex Wang
14:20~15:10CD03Virtuoso What's New 6.1.4 - Virtuoso Advancing the Art of Custom Design Kevin Tsai
15:10~15:40Break
15:40~16:30CD04Advanced 32/28nm Node Challenges & Solutions - Enabling Fastest Time-to-VolumeEason Lin
Functional and System Verification & Z+ k1 G$ y0 F: [3 t4 c+ h
(Ballroom C, 10F)
11:00~11:50FV01Predictable System RealizationMichael McNamara
11:50~13:30Lunch
13:30~14:20FV02* N! G. b" w' {) @$ o4 x7 p7 R
Cadence TLM Design & Verification with C-to-Silicon Compiler		Mark Warren
14:20~15:10FV03Cadence TLM to GDSII flowRich Owen
15:10~15:40Break
15:40~16:30FV04Cadence TLM Verification Cadence Expert
Digital Implementation " o! x* Z+ k* O( l
(Ballroom A, 10F)
11:00~11:50DI01Digital Implementation Update at TSMC Reference Flow 11 Cadence Expert
11:50~13:30Lunch
13:30~14:20DI02DoT/MSoT for Mixed Signal Demo Mladen Nizic
14:20~15:10DI03EDI System Roadmap: Encounter Digital Implementation System - Enabling "More than Moore"Wei Lii Tan
15:10~15:40Break
15:40~16:30DI04EDI System 9.1 UpdateCadence Expert
Logic Design - c3 u) ~, T/ {, ?
(Ballroom B, 10F)
11:00~11:50LD01Cadence Logic Design Product RoadmapYoon Kim
11:50~13:30Lunch
13:30~14:20LD02Phyical Predictability in RTL Compiler SynthesisMark Ou
14:20~15:10LD03Conformal ECO DesignerB. C. Shih
15:10~15:40Break
15:40~16:30LD04Can your spreadsheet do this ---- Innovative applications of pre-RTL chip planningAnis Uzzaman
System and IC Packaging ! `6 d8 ?# x0 M7 T- \& W! a/ ?1 @
(Meeting room C, 13F)
11:00~11:50SPB01SiP and 3DIC/TSV Design in TSMC Reference Flow 11.0& b- b6 q- R2 J* u; \" F, x9 z
Mike Peng,
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11:50~13:30Lunch
13:30~14:20SPB02What's New Update for 16.3 Allegro Package Design and SI Simulation?

Joseph Kao  q- d$ n5 W" o# t) w
Thunder Lay

14:20~15:10SPB03Distributed Co-design for IC-Package-BoardThunder Lay
15:10~15:40Break
15:40~16:30SPB04Design issues from IC to package: Managing Package Outsourcing EngineeringKevin Liu
16:30~16:45Lucky Draw(Ballroom A, 10F)

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