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標題: Which verification IP products are you using for your current design? [打印本頁]
作者: globe0968    時間: 2013-9-5 02:17 PM
標題: Which verification IP products are you using for your current design?
Check all that apply, or if you don't know?
作者: sophiew    時間: 2013-11-19 04:45 PM
新思科技推出ARC HS處理器  因應下世代嵌入式數據和訊號處理系統(Embedded Data and Signal Processing Systems)6 ]; A7 q# z0 j, k, p
可達到最大之DMIPS/mm2面積效能以及DMIPS/mW執行效率 ; ?# s6 E4 g4 ]- r. O

' v, m" v# M' P+ q- i4 O" w重點:
* [/ q5 e$ {6 X7 w" t% b1 q·      DesignWare ARC HS34和HS36核心為建構在具可擴充性的ARCv2架構之高速低功耗處理器的新系列產品。
0 `4 C) T) P7 e/ _4 |) E" c·      在一般28奈米製程中，新的32位元核心能提供超過4200 DMIPS的處理能力，而且只耗用低於85毫瓦的功耗以及0.15 mm2的矽面積。$ H/ i7 u3 X& }1 v
·      其高度可配置性讓用戶能為特定的嵌入式應用(如連接網型家電、汽車、SSD和家用網路等) 客製核心。, ]5 g' I) s  _' Y2 y" D% J  s
·      客製指令讓設計人員將專屬硬體加速器整合至處理器中，達成整體系統效能的優化並減少記憶體使用空間。3 f- a# o- T2 x3 t. D" _
·      其開放架構支援記憶體的緊密耦合以及支援直接映射(direct-mapped)的周邊裝置，可降低系統延遲(system latency)和減少功耗及矽面積。" h, i4 T- y* d9 P) _& h8 p3 ?- A
·      軟體開發工具、作業系統以及來自新思科技和第三方合作夥伴的中介軟體構成廣泛的產業生態系，可加速以ARC為基礎之系統設計。 - i5 h) M: I, \0 O* Q( ~' H

  h$ H0 A, w/ i8 J8 m; Y) h3 V) i(台北訊) 全球晶片設計及電子系統軟體暨IP領導廠商新思科技(Synopsys)近日宣布，推出全新DesignWare® ARC® HS處理器系列產品。32位元ARC HS34和HS36處理器是目前最高效的ARC處理器核心，在一般28奈米的矽製程中，能以高達2.2 GHz的速度提供1.9 DMIPS/MHz的處理能力。新的HS處理器能讓功耗效率(DMIPS/mW)及面積效率(DMIPS/mm2)達到最佳化，同時執行高速數據和訊號處理作業，能充份運用在SoC中使用的嵌入式處理器，以符合固態式硬碟(solid-state drive，SSD)、連網型家電(connected appliances)、汽車控制器、媒體播放器、數位電視、機上盒(set-top box)、家用網路等產品的需求。
作者: sophiew    時間: 2013-11-19 04:45 PM
Abilis Systems公司執行長Yves Mathys表示：「為了符合日新月異的數位電視市場需求，我們的設計團隊在低功耗、低成本條件下，達到高效能的要求。新思科技的ARC HS處理器進一步提升我們嵌入式設計的效能及功耗表現，並且還能大幅縮減晶片面積。同時，藉由ARC軟硬體開發工具以及第三方的支援，讓我們的設計能依照既定時程進行，這也是能如期推出新的數位媒體產品的關鍵。」 # I8 W- ]! M( `; ], }

* V' v% \4 R" k5 Y' o可擴展效能 (Scalable Performance)" Z& n# |2 R5 D# T9 R
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新的ARC HS處理器系列使用新一代ARCv2指令集架構(instruction-set architecture，ISA)，能在極低功耗下，實現高效嵌入式及高度嵌入式設計，同時使用的矽面積也相當精簡。運用於一般28奈米製程中，HS核心僅耗用0.025mW/MHz，且使用面積最小可達0.15mm2。該核心具備高速的10級管線(10-stage pipeline)，支援亂序執行(out-of-order execution)，進而將閒置處理器周期降至最低，且讓指令吞吐量(instruction throughput)達到最大。精密的分支預測(branch prediction)以及後期ALU能提升指令處理的效率。為加速數學函數的執行，ARC HS處理器讓設計人員可以選擇執行硬體整數除法器( integer divider)、64位元乘積指令、乘積累加(multiply-accumulate，MAC)、向量加法和向量減法，以及可配置IEEE 754浮點算數單位(單/雙精確度或兩者兼具)。
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% D2 v$ e" r5 x2 i: J與前一代的ARC核心相較，ARCv2核心可提升程式碼密度(code density)達18%，進而減少記憶體需求。新的64位元雙倍載入/雙倍儲存之非等齊記憶體(unaligned memory)存取能力可加速數據移轉，透過這項功能，HS處理器能支援緊密耦合(close coupled)記憶體以及指令和數據緩存(只限HS36)。此外，針對需要更高階的記憶體可靠度和記憶體保護的應用，客戶也能額外選擇適用於處理器中所有記憶體的錯誤校正碼(error-correcting code ，ECC)硬體。
作者: sophiew    時間: 2013-11-19 04:45 PM
Linley Group首席分析師Linley Gwennap表示：「如果不考慮功耗和電晶體預算，要設計出高效能的處理器並不困難。但處理器若要滿足面積小、有效率，能提供足夠效能因應當前需求，同時還要留有空間以因應未來的成長，設計難度便提升很多。為了讓用於嵌入式應用的ARC HS核心達到最佳化，新思科技提供彈性極大、能讓SoC設計人員自行調整的CPU，在使用較少電晶體和功耗的情況下，達到高吞吐量。它的強大功耗效率以及低成本，可有效協助嵌入式系統的開發人員。」
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可配置和延展性 (Configurability and Extensibility)
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具備高度可配置性的ARC HS處理器可協助設計人員調整其SoC核心的每個資料事例(instance)，以達到效能、功耗和面積的最佳平衡。用戶能將指令定義擴展至處理其專屬硬體加速器整合的處理器管線，如此可大幅提升特定應用(application-specific)的效能，同時降低功耗及所需的記憶體。原生的ARM® AMBA® AXI™ 和AHB™標準介面能進行32位元及64位元兩種交換處理的配置，使系統吞吐量達到最大。透過單週期存取(single cycle access)，SoC的周邊裝置能直接映射(direct map)至CPU，如此可減少系統層級的延遲並讓硬體整合達到最大化。HS34與H36核心能實現處理器與系統的效能優化，藉此讓設計人員設計出具差異化的產品，同時降低實作成本。 " y7 ?2 b; }0 j3 @, Y. W0 q

* t  ]8 }$ P6 y9 i  F& F0 e' N強大的軟體開發支援+ P# e7 ~: D- P& {; `

) }+ t& `- I2 z) r; o2 V新思科技MetaWare開發套件支援新的HS核心，這套完整的解決方案用於進行ARC處理器中嵌入式軟體的開發、除錯(debugging)及優化。該套件包括可產生高效率程式碼的優化編譯器、讓軟體中的可見性(visibility)達到最高的除錯器，以及作為預先硬軟體開發的快速指令集模擬器(instruction set simulator ，ISS)。另外也提供100%週期正確(cycle-accurate)的模擬器(simulator)，用以達成設計優化及供驗證使用。支援HS處理器系列的作業系統(OS)包括新思科技的MQX  RTOS── 能實現最佳確定性反應時間(deterministic response time)及記憶體效能的全功能即時作業系統(real-time operating system)。使用者可從參與「ARC存取計畫」(ARC Access Program)中之合作夥伴，取得由第三方所提供的額外軟硬體工具，方便進行ARC HS處理器的軟體開發。這些軟硬體包括：由Ashling Microsystem及Lauterbach提供的先進除錯工具，以及Express Logic提供的ThreadX RTOS。& ?3 `) }) @1 |7 {3 G

0 f, K, }+ R+ ]新思科技IP及系統行銷副總裁John Koeter表示：「每年ARC 晶片的出貨量超過13億個，我們深知新世代電子裝置所需的處理器必須同時達到高效能與低功耗、低面積的目標，而ARC HS處理器系列可有效符合這些需求。HS34與HS36核心的推出，代表ARC產品組合的大幅精進，也顯示新思科技致力於擴展ARC的產品規劃，以滿足設計人員對於嵌入式設計不斷改變的需求。」
作者: globe0968    時間: 2014-2-14 02:05 PM
Principle Verification Engineer
  }  D+ L  f( i7 i! `6 G7 U公      司：One world top EDA company
2 {$ C+ f4 }! b1 ~工作地点：北京4 C3 }9 z0 _8 J. p# p, `

+ j, [: x8 k) TPosition Description:  , p8 G5 i& w7 m8 Z; E/ R7 V) i* A
Deliver/implement advanced verification solutions by utilizing XX’s Incisive Verification product portfolio. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.
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Specific duties include: ( ?9 G% f! k/ i% P* o( }
--Deep understanding on ASIC/SOC design flow
, R/ F; x' i/ p# t# P  G/ g--Excellent knowledge of advanced verification methodology like eRM/OVM/UVM
. s1 F5 `' s  K2 Q5 F–Familiar with XX’s Incisive Plan to Closure Methodology (IPCM) $ z0 Z5 n6 o, v% A) z. O! y
--Proficiency in System Verilog, System C and/or e (Specman) ( w# n& C* {+ D. c' ?/ u' _
–Developing and using Verification Components (eVC,OVC,UVC,VIP)   u/ W  z, B2 ?4 i
–Developing and using assertion based verification and formal analysis methods
4 }8 x" G+ R. T- V3 {8 x--Skilled in scripting language,such as Perl,C shell,Python,Makefile
1 M2 x; |5 @' M9 E–Assessing the project verification requirements
. c7 ?2 F5 j9 W( j# \5 i–Operating in a lead role regarding architecting and implementation of project verification environment/solution.! X1 i8 [$ d# Y! R5 i
–May coordinate/lead others within the scope of a defined project
作者: globe0968    時間: 2014-2-14 02:05 PM
Position Requirements:  * E: ?) h/ a7 D) r1 V& |
Essential Qualifications:  
( W2 q. X" Z' w0 I5 a6 y- BS degree with 5+ years of applicable experience,MS degree with 4+ years of applicable experience in electrical engineering,microelectronics,comparable engineering science or solid state physics. 5 B7 v+ e* @" g4 Z
- Essential that the individual demonstrates strong communication,verbal and written. Requires good communication skills in English.
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Desirable Qualifications:  
' t$ D- ~3 ~8 L- A minimum of four years relevant experience in industry.
; {9 H+ e4 U- L, ~2 d4 C- d- Will have demonstrated hands-on experience and expertise with Cadence verification design tools or equivalent tools, flows and methodologies required to execute a verification project.% h4 n! ?, N0 d: C/ W. K
- Will have demonstrated successful completion of 6+ verification projects as an individual contributor ) j6 R2 U" h9 ]2 e! S
- Will have DDR project verification experience
作者: globe0968    時間: 2014-2-14 02:06 PM
Integration Engineer( j, C; z: d/ k! @/ p
公      司：A MEMS IP service Company
/ R0 G. c& d9 u2 l. x) g+ t8 ~+ _0 f工作地点：苏州
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Job Description:
: F; G/ O, |7 v/ C% F- m3 s1 e$ O·         MEMS Technical/Integration expert for consulting customer projects  
8 g; v0 `2 Y% g' W$ a·         Hands-on work doing  
  E9 y9 K5 x; c# E, v/ m8 yo    MEMS process engineering, process integration, simulation and basic design
3 }$ B( M. i! Z5 R- ko    DOE design, Data Analysis and Report Generation ' t& J. ^: I  U" }" Y
o    MEMS bench testing and device testing - t8 ~7 M" V# |+ M  W8 a
o    Project Planning/ Scheduling  
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" J( Q/ W; V+ m' z% r! t" EJob Summary: 6 Y( c) \$ e& Q
·         The engineer will serve as a MEMS Integration/Test engineer to support customers in demonstrating concept and feasibility of new MEMS devices and technology using company’s IC and customer IP.# A' @7 o# E- K& z. g3 c
·         The engineer will use, and help customers to use, the Company’s IC Technology Development Process (TDP).) |1 d9 H, t" c3 T) i% p
·         The engineer must have a strong background in MEMS process, integration, bench test, inline e-test, test program creation and have a strong understanding of test requirements/parameters.
# R/ C/ }+ D2 R9 m4 j- k·         The engineer will help with basic MEMS design and simulation tasks.  $ M# p( q" z% S3 \' h& K. m
·         The engineer must be aware and sensitive of IP protocols to accomplish tasks including protection of foreground IP of the customer and development of foreground IP for company’s IC following contractual obligations. * z$ h6 ^, [6 r  }1 a1 z( ~( ~* J
·         The engineer is expected to work collaboratively with the customer in order to establish detailed project plans and deliverables, and to conduct engineering work with the customer.
作者: globe0968    時間: 2014-2-14 02:06 PM
Key Tasks/Duties/Responsibilities of this Position:
1 c* X# g3 d: u& Z+ Y5 J1 h- P$ k·         Serve as a technical expert to the customer by helping them plan and carry out engineering work required to make the customer product successful and manufacturable.
# Z* h5 M& k& E# T·         Create reports and present the results to the customer, writing summary reports and presentations, and attending selected technical conferences.: H: A' Q5 R+ ~" g
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Requirements
) o/ }. a5 l) R: ~·         B.S. (M.S. or PhD preferred) in Materials Science, Electrical Engineering or Physical Sciences
9 K2 E3 w7 Y: {* K/ S) |$ Z·         Strong ability to read, write, and speak English and Mandarin 7 n5 }$ `/ t6 [6 B' k- \% U( O
·         Experience as a consulting engineer would be very desirable.
. C; w0 }& ~: W4 A·         Experience doing MEMS device modeling using ANSYS, Coventor, or other similar tools would be very desirable.
0 i8 g' U2 q; Y·         Experience with basic MEMS device design CAD tools would be very desirable.
9 }+ V  K3 p3 J8 ~  |·         Requires > 7years’ experience in advanced MEMS/semiconductor process and integration technology development and testing.   \; z  a  o+ B1 l( W- z
·         Requires deep knowledge of advanced MEMS semiconductor processing, integration and device design, and process flow creation and electrical result/Failure analysis evaluation.
. E5 j& _2 {# i/ \7 b1 G·         Background in device physics and experience with process and device simulation are helpful. ! G# w, A' K: ~  J/ S& N

' ~/ D$ O' Q! d/ g7 ^/ C3 t8 m·         Requires:  : A9 ^6 J5 s, S
o    Strong ownership/responsiveness in a customer environment as a consultant
/ f. i7 w, ^# L9 Fo    Strong technical team direction skills
1 U4 l0 n, q3 P( |4 a2 Io    Good data analysis/statistics skills  
+ B6 _& ~7 h* Q; a3 j6 `! ao    Good oral/written communication skills in English and Mandarin
. d- i# G! S! B$ c' D·         Requires ability to communicate and interface with all levels of management in customer organizations.
作者: ranica    時間: 2014-6-4 09:11 AM
Integration Engineer
8 C5 q* B9 G- ?6 [% Z. [& J! u! O3 y) t& g  O7 p9 z8 c* r; M
公      司：A MEMS IP service Company7 ]# d( {! Z& Z
工作地点：苏州+ O, \1 {" P6 [; _1 |/ y
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Job Description:
+ T6 x0 S5 F& q, ]- N·         MEMS Technical/Integration expert for consulting customer projects  
7 k! X5 M# @% H' N* {8 ?4 b·         Hands-on work doing  % }1 b, z9 Q9 ]6 ?+ E
o    MEMS process engineering, process integration, simulation and basic design
& x& h2 k* J4 o2 a. go    DOE design, Data Analysis and Report Generation 0 Q) J  Y# u# w6 r5 v! x# Q: {0 g
o    MEMS bench testing and device testing 7 E9 A" U8 Z9 g4 k  a
o    Project Planning/ Scheduling  
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Job Summary:
; F, G% K5 a# |4 d·         The engineer will serve as a MEMS Integration/Test engineer to support customers in demonstrating concept and feasibility of new MEMS devices and technology using company’s IC and customer IP.2 c; {# v! a( e% M5 u
·         The engineer will use, and help customers to use, the Company’s IC Technology Development Process (TDP).( l9 c5 y2 _! ~- T
·         The engineer must have a strong background in MEMS process, integration, bench test, inline e-test, test program creation and have a strong understanding of test requirements/parameters. / I! f5 E# B1 B; g# a- |
·         The engineer will help with basic MEMS design and simulation tasks.  " Y; S0 w+ e7 M- Z( K% m* b
·         The engineer must be aware and sensitive of IP protocols to accomplish tasks including protection of foreground IP of the customer and development of foreground IP for company’s IC following contractual obligations. , b( Q$ U9 w9 p: v
·         The engineer is expected to work collaboratively with the customer in order to establish detailed project plans and deliverables, and to conduct engineering work with the customer.
作者: ranica    時間: 2014-6-4 09:11 AM
Key Tasks/Duties/Responsibilities of this Position: ; `$ G3 r8 }) p! s
·         Serve as a technical expert to the customer by helping them plan and carry out engineering work required to make the customer product successful and manufacturable./ W1 K/ V( g) Q
·         Create reports and present the results to the customer, writing summary reports and presentations, and attending selected technical conferences.
& C" n1 J4 t: `# W* L职位要求
2 x1 j" b+ r$ b* D* VRequirements
; R5 M- |+ ~, \) \- U4 e# v·         B.S. (M.S. or PhD preferred) in Materials Science, Electrical Engineering or Physical Sciences 5 v& N* X& J: _9 `  N: ~4 r6 c
·         Strong ability to read, write, and speak English and Mandarin
% T& j( l% f6 S5 B: ]·         Experience as a consulting engineer would be very desirable. ) `6 x, \& h- f- \: ^, {9 m% d4 O! C
·         Experience doing MEMS device modeling using ANSYS, Coventor, or other similar tools would be very desirable./ K4 y, G$ I2 Z8 l7 q
·         Experience with basic MEMS device design CAD tools would be very desirable.
8 p& ~3 F- i# g* J0 k0 a5 Y·         Requires > 7years’ experience in advanced MEMS/semiconductor process and integration technology development and testing.
/ @. a4 Z( |. d% x, E·         Requires deep knowledge of advanced MEMS semiconductor processing, integration and device design, and process flow creation and electrical result/Failure analysis evaluation.
$ k: N$ r- K% M' H: F·         Background in device physics and experience with process and device simulation are helpful.
1 C+ m% m6 ^1 e$ W2 Y9 r$ c
: [' e- M# K% J1 f1 a: Q·         Requires:  
' |# P1 h( F& D9 r3 L- v  ro    Strong ownership/responsiveness in a customer environment as a consultant
% O' A8 |4 H) b. O" x- Do    Strong technical team direction skills 5 ^0 h+ I# A+ r2 D( A5 Y7 y# ~! P
o    Good data analysis/statistics skills  7 J1 n3 R0 U! P- C; V5 `, `7 |. }
o    Good oral/written communication skills in English and Mandarin
+ t, L" m- W/ X' ~% K·         Requires ability to communicate and interface with all levels of management in customer organizations.
作者: ranica    時間: 2014-6-4 09:12 AM
Integration Engineer% c3 v4 w* h5 }* \
0 C3 g" X$ F  I$ q( P0 w2 ~4 p2 N
公      司：A MEMS IP service Company; E; w7 j6 f/ O2 z8 a# i4 ^! A
工作地点：苏州! @3 m5 ]8 l! }+ ?
. q- U6 B7 q* r# j
Job Description:
: k; i% m% V: ~3 y5 k·         MEMS Technical/Integration expert for consulting customer projects  - b& o: S* A' ?4 T9 o
·         Hands-on work doing  
7 A+ ]3 s; b# Q$ {o    MEMS process engineering, process integration, simulation and basic design / E5 P3 q0 G( }7 o
o    DOE design, Data Analysis and Report Generation , Q) O5 n4 \$ f9 {' ~* v
o    MEMS bench testing and device testing   l6 H0 `/ X% G) q  j2 b' X
o    Project Planning/ Scheduling  
; {8 p" y: l& _( l3 J; a5 G; ?9 }, e
Job Summary: 1 m8 g9 x. t, [6 g3 U' D
·         The engineer will serve as a MEMS Integration/Test engineer to support customers in demonstrating concept and feasibility of new MEMS devices and technology using company’s IC and customer IP.* z4 J) H# X* G4 g" A* U9 W
·         The engineer will use, and help customers to use, the Company’s IC Technology Development Process (TDP).
# w: M5 p. N( k+ G·         The engineer must have a strong background in MEMS process, integration, bench test, inline e-test, test program creation and have a strong understanding of test requirements/parameters.
  Q! m! w% D0 t" z·         The engineer will help with basic MEMS design and simulation tasks.  
  K2 B5 I" ^: F·         The engineer must be aware and sensitive of IP protocols to accomplish tasks including protection of foreground IP of the customer and development of foreground IP for company’s IC following contractual obligations. - V6 g/ b+ a1 U7 _
·         The engineer is expected to work collaboratively with the customer in order to establish detailed project plans and deliverables, and to conduct engineering work with the customer.
作者: ranica    時間: 2014-6-4 09:12 AM
Key Tasks/Duties/Responsibilities of this Position: $ \& l6 J  `6 Q7 O) H* M% {% B) A
·         Serve as a technical expert to the customer by helping them plan and carry out engineering work required to make the customer product successful and manufacturable.
) u3 D# I4 ^; _0 t7 c·         Create reports and present the results to the customer, writing summary reports and presentations, and attending selected technical conferences.
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) p9 w3 Z5 [0 P! M2 V, LRequirements
) J4 u$ c# f  q4 w% \: d( P& V) G·         B.S. (M.S. or PhD preferred) in Materials Science, Electrical Engineering or Physical Sciences
2 C* @0 u( j" \' G3 y·         Strong ability to read, write, and speak English and Mandarin ! |) r  R0 w8 y3 v4 n7 {& k
·         Experience as a consulting engineer would be very desirable.
4 H) w" o+ q0 ^·         Experience doing MEMS device modeling using ANSYS, Coventor, or other similar tools would be very desirable.
( u; L% L/ L1 g4 A- I·         Experience with basic MEMS device design CAD tools would be very desirable.
3 b; [* p, e- i- D·         Requires > 7years’ experience in advanced MEMS/semiconductor process and integration technology development and testing. / d2 n. Q) @2 g( a/ x9 n
·         Requires deep knowledge of advanced MEMS semiconductor processing, integration and device design, and process flow creation and electrical result/Failure analysis evaluation.
6 o/ P8 @7 j. L·         Background in device physics and experience with process and device simulation are helpful.
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( W5 q4 p6 M3 r/ p5 F·         Requires:  # W) u. l" f/ }0 @) x, A1 q; v
o    Strong ownership/responsiveness in a customer environment as a consultant
8 l. Q1 J5 W" h, s; a3 ^: G5 Fo    Strong technical team direction skills 5 L& L: t$ ~: d( v& x: `
o    Good data analysis/statistics skills  * J! j7 @1 A3 C3 G3 ]) s6 n8 d
o    Good oral/written communication skills in English and Mandarin
0 L/ d' R; j! U/ Y$ F' E  R0 m# ~2 t" G·         Requires ability to communicate and interface with all levels of management in customer organizations
作者: ritaliu0604    時間: 2014-6-18 06:32 PM
本帖最後由 ritaliu0604 於 2014-6-18 06:34 PM 編輯 8 [! w3 R" u7 g- `

* j( a( [+ M8 |5 L* y新思科技全新矽驗證DesignWare USB 3.0和USB 2.0 femtoPHY IP 能減少50%的晶片設計面積
8 y, I9 r# `9 A( f2 s; U: i應用於14/16奈米FinFET及28奈米製程之PHY實體層具有較少的矽足跡，可減少開發消費性產品、行動裝置、儲存及網路應用的矽成本9 S0 J+ E$ _7 C8 G
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重點摘要：
9 l9 ^# z# ~! u$ d, A# K. e9 M·         DesignWare USB 2.0 femtoPHY IP面積小於0.2平方毫米，而DesignWare USB 3.0 femtoPHY小於0.5平方毫米，讓設計人員可縮減實體層(PHY)使用面積，並降低整體的矽成本。% W: v0 G5 j: M- \0 B
·         DesignWare USB 3.0 femtoPHY全面支援USB 2.0，能與全球數十億裝置相容。5 N* [- t9 T3 Z. S. y, V1 N, c
·         節能加上資料保持功能，可延展電池續航力同時確保資料留存；而支援USB電池充電1.2版(USB Battery Charging v1.2)的規格，則能有效率地為可攜式裝置完成充電。
0 H% S0 Z6 ^- U2 f, o! u·         DesignWare USB femtoPHY的針腳數(pin count)縮減設計，將SoC周邊的面積和寬度縮減至最小。
: R% ^! |1 G, {9 C) p6 V·         DesignWare USB femtoPHY在28與14奈米FinFET製程中皆取得客戶矽驗證。( m2 _# q" P  n) N. {; K5 I$ V
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[attach]20021[/attach] 5 ^1 w' c) q( ]; O2 P; [
此眼睛般的圖示代表在14奈米FinFET製程技術中，新思科技DesignWare USB 3.0 femtoPHY矽晶所展現的絕佳效果和優勢。
作者: ritaliu0604    時間: 2014-6-18 06:33 PM
(台北訊) 全球晶片設計及電子系統軟體暨IP領導廠商新思科技(Synopsys)近日宣布，全新的DesignWare® USB femtoPHY IP成功將USB PHY實作面積縮小達50%，並能減少USB PHY的矽足跡以及針對28和14/16奈米FinFET製程的晶片設計成本。在28與14奈米FinFET矽晶中，DesignWare USB femtoPHY展現了強大效能，讓設計人員在先進製程技術中也能實際應用IP，並降低系統單晶片(SoC)的設計風險。而因應晶片設計面積極小化的需求，最佳化的DesignWare USB 3.0 和USB 2.0 femtoPHYs，能滿足智慧型手機、平板等行動裝置以及數位電視、儲存和網路等大量消費性應用產品的嚴格要求。
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DesignWare USB 3.0 以及 USB 2.0 femtoPHY IP (包括DWC SS USB femtoPHY Samsung 14nm FinFET and DWC HS USB femtoPHY Samsung 14nm FinFET)已通過多項由USB開發者論壇(USB Implementers Forum, USB-IF)所進行的相容性測試，包括5V耐受度(tolerance)和3.3V訊令傳輸(signaling)；其所具備的卓越效能，對於採用USB-IF規格的系統配置來說是一大福音。此外，DesignWare USB femtoPHYs也支援完整的USB實作，提供可應用於廣泛SoC設計的系統架構。DesignWare USB 3.0 以及 USB 2.0 femtoPHY IP皆支援、高速、全速和低速運作，以及主機端(Host)、裝置端和OTG(On-the-Go)配置。同時，DesignWare USB 3.0 femtoPHY 還支援 SuperSpeed USB (USB 3.0)。
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三星電子晶圓行銷副總裁 Shawn Han表示：「基於長久以來使用DesignWare USB IP的成功經驗，這次我們利用高品質的DesignWare USB 3.0 和USB 2.0 femtoPHY IP達成一次完成矽晶設計(first-pass silicon success)。此次在三星電子晶圓廠完成製造流程的DesignWare USB femtoPHY IP，是第一個通過USB-IF認證的14奈米FinFET矽晶。客戶採用面積大幅縮小的PHY後，將能提升SoC設計的競爭力，同時也簡化額外的USB連結。新思科技的DesignWare femtoPHY滿足大量行動裝置和消費性應用產品在成本、功耗、效能及上市時程等需求；而這些都是讓我們能成功因應快速變化的市場需求的重要關鍵。」
作者: ritaliu0604    時間: 2014-6-18 06:33 PM
新思科技所開發的USB 3.0 和USB 2.0 femtoPHY IP，能讓設計人員在不犧牲USB認證所要求的功能情況下，為其設計的應用選擇最理想的實作方式，例如，要求高效能的設計，能藉由SuperSpeed USB (USB 3.0)的規格，有效利用USB 3.0 femtoPHY的 5.0 Gbp數據傳輸率；而對效能要求較少的應用，則可藉由Hi-Speed USB (USB 2.0)規格，執行USB 2.0 femtoPHY的 480 MHz數據傳輸率。兩種DesignWare USB femtoPHY都能減少SoC周邊所需的針腳(pin)數，以進一步降低SoC的面積和成本。透過節能(power down)功能，當PHY未運作時，可將其設為待機狀態，一方面降低電池消耗，同時保有PHY的全部使用狀態，有助於快速、正確的恢復開機模式。此外，DesignWare USB femtoPHY還支援業界普及的USB Battery Charging 1.2版以及USB OTG 2.0版協定。 $ B- e  G; M+ Y; V4 o& C1 g% B! E$ q3 u
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USB開發者論壇總裁暨營運長Jeff Ravencraft表示：「十八年來，新思科技一直是USB-IF的活躍會員之一，藉由不斷開發IP產品，讓USB 3.0 和USB 2.0介面能輕易地整合和應用。而新思科技全新且面積較小的DesignWare USB 3.0 和USB 2.0 femtoPHY取得USB-IF的認證，意味著該產品能滿足USB-IF相容性標準，並且符合相對應的規格，協助晶圓製造商，能順利將這項技術納入他們的SoC製程中。」
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  u  B9 [7 ?, I: r: O新思科技IP暨軟體原型行銷副總裁John Koeter表示：「透過新思科技的解決方案，SoC設計人員已在3,000多件設計和超過100個製程技術中，完成USB介面開發，鞏固了新思科技10多年來位居全球USB IP主要供應廠的地位。新思科技IP技術團隊及為先進製程提供高品質IP專業技術的佳績，讓設計人員在晶片設計中，具有整合能滿足各項應用迫切所需IP的能力。隨著DesignWare USB 3.0 和USB 2.0 femtoPHY IP的推出，以及成功應用在FinFET矽晶技術上做為後盾，讓我們能協助客戶滿足業界需求，設計出更小、更低成本及更高效能的SoC。」
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% ^9 L- O" @8 Y上市時程
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DesignWare USB 2.0 和USB 3.0 femtoPHY IP已應用在業界主要的14/16奈米FinFET和28奈米製程節點。



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