The MathWorks Announces EDA Simulator Link DS for Synopsys VCS MX
/ O; B) A; K- d/ e7 |5 M | 3/24/20083 _% }, i( m- y, h1 N
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Synopsys to Acquire Synplicity+ Y5 k0 k) I, J I9 s3 g; e# G
| 3/21/2008+ ]8 \ ~4 y. [ M4 K
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Synopsys IC Compiler Routing Qualifies for TSMC's 45-nm Process3 o+ T2 D6 [1 ^+ C% D6 e& j$ c
| 3/17/2008
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Synopsys Launches HSpice Integrator Program With 25 Founding Members1 C, k! l, u! ?( A% K" j
| 3/11/2008
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Synopsys Announces Multi-Core Initiative to Accelerate Design Time-to-Results
4 f& K( \5 V0 S5 g8 p% {, o& H* [ | 3/10/20084 o) X b$ r, _# O5 V6 `8 j8 Z* q
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Synopsys HSpice Delivers New Technology to Accelerate Circuit Simulation Performance
5 v- j2 ^1 |" @( S3 o+ i; T/ G | 3/10/2008
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Synopsys Enters Embedded Memory Market with Highly Differentiated IP ~1 {; Z& `4 v$ p2 O X$ ?! l8 I
| 3/6/2008' s! y3 T* q9 k" Z
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PrimeYield LCC Enables Litho-Clean Tapeout for LG Electronics HDTV Application Chipset+ J4 p0 N- l9 H
| 3/4/2008
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Synopsys and SMIC Deliver Enhanced 90-nm Reference Flow to Reduce IC Design and Test Costs
+ |1 ~( Z; H7 ] | 2/27/2008- k( ~0 H7 r7 z. D2 Z9 f
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Synopsys Introduces Concurrent Hierarchical Design System with Latest IC Compiler Release2 C$ {5 d3 L2 h$ y0 g
| 2/27/2008& W) e: c! _: C$ u$ r0 M0 \" @ ]
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Synopsys Unveils Proteus Pipeline Technology0 \+ C! f! G) C5 w" q3 l3 ?/ r
| 2/27/2008; y" T, o9 _4 k" Z
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Synopsys Introduces the Eclipse Low Power Solution
# k- Y/ S% ^/ G3 | | 2/25/2008' W/ o0 y S# V0 E# \. p& `% k c
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Radiospire Standardizes on Synopsys VCS and VMM Methodology for Next-Generation AirHook Chipset Designs) L: O) Y- Z8 |; O1 Y6 g8 u$ m( a
| 2/15/2008* r& l9 {2 X* I1 o. j& F
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Synopsys TetraMAX ATPG Solution Boosts Structural Test Quality at STMicroelectronics
/ D2 U% V: Z: X4 f$ u | 2/15/2008. w% B) X6 ^" Z+ O' K1 ]" i
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LG Electronics Increases Quality of HDTV Chip Using Synopsys Test Solution
( q! D- j: U6 [' x) { | 2/13/2008
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Synopsys Expands USB IP Portfolio with New IP for Link Power Management and High Speed Inter-Chip Standards
& [+ G- }) o$ Q+ `* G | 2/4/2008" [7 R% U& Q- y9 X9 {6 ~
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Synopsys' DesignWare DDR Protocol Controller IP Integrated Into Arteris' Network-On-Chip Interconnect Solution
+ k& s6 y: e3 e; u6 [0 S$ J | 1/30/2008& W% `! c0 b3 I/ n, _7 f
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Synopsys and Acceleware Deliver Hardware Accelerated Solution for Design of Optoelectronic Devices
+ i2 o# ]4 u' O | 1/22/20082 h+ L) e' p+ X( U* R: c
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Magma, Mentor Graphics and Synopsys Deliver Unified Power Format-Based Products% }) c4 N; r, l0 L. O
| 1/21/20088 h3 x. w$ f4 z1 b1 d. T% f* B0 e
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Synopsys IC Compiler Used by Matsushita for First 45-nm SOC Design Tapeout
4 b. @2 g# k- D, ~+ q( O' G8 M | 1/21/2008" S' }; [& i W7 R8 r
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STARC Adopts Synopsys PrimeTime VX as the Variation-Aware Timing Tool for Its STARCAD-CEL Methodology
8 R c! }/ a/ Y$ i$ G1 K5 w0 p5 E. X | 1/14/2008: w9 z0 w: o! K3 L8 {
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Silicon Canvas Laker Environment Integrates with Synopsys Hercules Physical Verification Suite4 ~- Y$ }, J, \& ]3 v; h2 p% r! ?
| 1/8/2008
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iC-Haus Converts to Synopsys HSIM-XA for Its Zero-Defect Mixed-Signal Chips+ Y/ U4 @ Z; Y! f Z: w, u/ ]+ L
| 1/7/2008$ P/ L+ {1 O! H/ {) w+ L; X
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