hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs
; W  Q& n. C* r8 v2 S" u1 \. [, A
0 w' `0 g0 N8 ^7 w0 s7 l& m要怎麼定義用
3 X7 \* i% Q% eplot LX??
) x' \; e" j# ?! B: ]0 p3 H  x& G
請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .

Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.
( W) C9 l3 d* y9 j9 c

For your reference.

0918429587

CAB_BS    LX28
+ ]7 e, R3 K: U) mCAB_BD   LX29
# L8 @7 {7 Y0 s4 l/ u2 w/ L
其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
這是 CGDBO  CGSBO CBGBO
. j; M1 v" M4 v1 l" y( J
不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
& v5 X* U# P6 mAn example for your reference...
3 v7 T: V1 e4 h7 _, w8 l
. W: m) B( p+ M0 g----------------------------------------------------------------
***** Gate Capacitance Plots *****
' U1 G$ t8 E* P9 O/ O& Y+ r9 @.lib 'your_component_model' lib_corner
0 q$ H3 O0 A; q9 y, J- ^.temp operational_temp
.option dccap=1 post
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
' \2 x' B0 S- X4 N) \5 Kvd n_drain gnd 0
0 h4 C2 n% Z: w% i! Fvg n_gate gnd 5
+ ^) P9 l* F; Avb n_bulk gnd 0
.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
+        CGD=par('-lx19(m1)')
9 a7 L/ S& E1 I$ d# {+        CGS=par('-lx20(m1)')
+ `( M- d* C" ~( \* U5 T  I+        CDG=par('-lx32(m1)')
( k9 p! j$ p8 e# O; a* j6 d. [- c- y/ a+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
4 u! h! y2 i; n0 K7 k# c% J0 l4 v# f+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
8 P; ^  e3 ?$ j3 a3 O.ends

----------------------------------------------------------------
Six capacitance are reported in the operating point printout
    cd_total = dQD/dVD
7 Y# v' d2 T- i7 V0 }3 H) L    cg_total = dQG/dVG
    cs_total = dQS/dVS
8 |/ w% H1 K" v( K5 t" Y' U% M: _    cb_total = dQB/dVB
6 N  l6 z; N3 y' a, K    cgs = -dQG/dVS
! j1 f, s. z1 K8 u4 W% j    cgd = -dQG/dVD
There capcitances include gate-drain, gate-source, and gate-bulk
4 E) ?) B& s3 k' |6 {8 p- }overlap capacitance, and drain-bulk and source-bulk diode capacitance.

# s, x: @/ T0 W% Z4 O- A0 pCGG = dQg/dVG
CGD = -dQg/dVD
CDG = -dQD/dVG

The MOS element template printouts for gate capacitance are LX18~LX23
and LX32~LX34.
; M+ ~$ g7 o( c; V- j% k! r
LX18(m) = dQG/dVGB = CGGBO
LX19(m) = dQG/dVDB = CGDBO
LX20(m) = dQG/dVSB = CGSBO

9 P% ^  j/ v+ l9 y" ]+ OLX21(m) = dQB/dVGB = CGGBO
LX22(m) = dQB/dVDB = CGGBO
3 [5 [1 c( l) v4 ]. OLX23(m) = dQB/dVSB = CGGBO
% x, ]) b6 W$ q7 w5 P' r' i+ I
7 P( i7 R) }  b( s, _2 fLX32(m) = dQD/dVG = CDGBO
6 h% n# F% H8 c! R' _& bLX33(m) = dQD/dVD = CDDBO
+ X. [% T6 T) `( {2 H9 aLX34(m) = dQD/dVS = CDSBO
: m  C8 c- O' T* Y
2 `* n2 y) [& i# r; c8 i6 M( ?3 h: d1 j6 wThe equation shown above is for an NMOS with source-bulk grounded
configuration. Refer to the user's manual for more detail ^^