hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs

* Z: t5 Q# X+ z& z要怎麼定義用
plot LX??

3 r* [. m6 F5 a" |請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .

Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.
9 S* P# p$ N! W
, K1 Y( j! L9 V
# ~) e; }1 Z* B2 q0 T5 {For your reference.

0918429587

CAB_BS    LX28
9 C- ^5 v8 F( p2 i7 K2 e) hCAB_BD   LX29
6 ?' j0 U  f, c2 _, \( t
1 G$ F- y+ H" y* T/ e$ k% c8 A6 i其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
+ Y* K/ C) f; `4 [2 ]. c# N- h- t這是 CGDBO  CGSBO CBGBO
$ `( _: _. q) p' a$ ~/ K! p7 n
不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
An example for your reference...
1 s& L2 i, V3 {; `1 O6 B
; v) M7 B2 |! u5 F% [+ g----------------------------------------------------------------
1 {. e0 }5 e2 p# l***** Gate Capacitance Plots *****
.lib 'your_component_model' lib_corner
.temp operational_temp
1 b4 A5 }5 ~, P6 |. T; p.option dccap=1 post
8 M/ J. M- O5 q& E" am1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
vg n_gate gnd 5
vb n_bulk gnd 0
.dc vd 0 5.0 0.1
  C/ S, ?' T1 g: M4 o) P.print   CGG=lx18(m1)
- C, ]" x$ z, L2 E9 |: x- Z+        CGD=par('-lx19(m1)')
+        CGS=par('-lx20(m1)')
9 r' ^* `, d- C0 l+        CDG=par('-lx32(m1)')
( q4 x' c9 b- S% {+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
8 _6 L. p9 O+ s+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
+ J1 I7 V7 ]% k' V) W9 A.ends

7 @5 J5 g" {  e----------------------------------------------------------------
, g- G" I( _& a. t* w* HSix capacitance are reported in the operating point printout
    cd_total = dQD/dVD
5 M4 q2 u8 n$ t  W    cg_total = dQG/dVG
% i( b' x" _$ `9 ~: G3 k$ h    cs_total = dQS/dVS
% T7 d1 N5 j  H( i    cb_total = dQB/dVB
" B5 u1 L6 @6 R0 p+ _    cgs = -dQG/dVS
    cgd = -dQG/dVD
There capcitances include gate-drain, gate-source, and gate-bulk
overlap capacitance, and drain-bulk and source-bulk diode capacitance.
  T4 \5 F( _/ J$ t6 d
CGG = dQg/dVG
& O1 W/ e9 P' I: E3 @! CCGD = -dQg/dVD
$ ]) r4 R: Z. F2 Z/ b% lCDG = -dQD/dVG

The MOS element template printouts for gate capacitance are LX18~LX23
and LX32~LX34.

, J8 C  p; m- a9 y5 g3 o4 I/ sLX18(m) = dQG/dVGB = CGGBO
& e  |6 Z, Q4 g- X! x: e9 P5 w$ FLX19(m) = dQG/dVDB = CGDBO
2 b0 Q9 X" v+ j* i+ \' XLX20(m) = dQG/dVSB = CGSBO

LX21(m) = dQB/dVGB = CGGBO
" V2 M& U0 ^! i+ I9 g' S) hLX22(m) = dQB/dVDB = CGGBO
4 @6 X) Y' }8 P/ O$ FLX23(m) = dQB/dVSB = CGGBO
: }  X5 k2 k8 v9 W) f2 }7 B
$ e- {3 h3 }; T0 J5 uLX32(m) = dQD/dVG = CDGBO
7 a/ ^6 m1 k# k- |7 |LX33(m) = dQD/dVD = CDDBO
8 v- J: R' X- l$ F# k9 l: L1 oLX34(m) = dQD/dVS = CDSBO
6 m4 m/ F- `3 M, a7 N, C- ]( E" k
' \( R3 i1 x4 Y) I3 I! L( cThe equation shown above is for an NMOS with source-bulk grounded
/ p2 Y* A6 W7 e) K! c' a9 {6 ?configuration. Refer to the user's manual for more detail ^^