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A Layered Verification Approach Applied to an AMBA-Based System

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1#
發表於 2007-7-5 09:27:40 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
It’s common knowledge that the verification
4 d: M! C( W7 J+ h; |1 h9 mstage for a given system is
  m0 J# x: O( {4 Taround 70% of the overall design
! p" r- }# Z. {: ?, V9 r+ weffort and schedule time. Reducing0 r; x/ i7 L1 e2 a. {" g
overall time spent in test creation and! U( d5 k. t9 B8 v3 T
design verification is a high priority.
3 _; ]7 E* t7 P! ASuccess in these two areas increases
( i! L; O4 i. gproductivity and helps deliver products
0 @: ~2 X8 I6 J( Y% n$ bto market faster. To achieve these verification- x1 e4 r1 a# ?# {
goals, engineers are constantly
9 a6 B9 v, o* G$ E+ Y( n! H5 t5 W* alooking for new and innovative ways to/ D' ^* E* R$ T3 s& p* ]
conquer the verification challenges that
! m. ^+ E+ l4 o: kface them.2 K9 [6 `, X' q1 m3 g, ~
This article discusses a layered verification
* m* _; S" P+ @! j% h4 l& I+ Happroach as applied to an AMBAbased
$ J% c$ u1 n" g* Zsystem component. The layered
; B* [: B! B& Xapproach is used to create a standardized
1 c* a. @) u9 n. o4 Cverification environment that can8 H; c* O/ Q: b! i
adapt as the design challenges% K! Y* ^( f+ [6 Z) z7 p; D
increase. Typically, reuse is very high; J1 h; N, m" K) `4 q$ f: N  d6 J7 ]
within an AMBA-based system because- J+ L; U/ _; V9 v& h
many new designs are based on earlier
* ~- _& M5 A5 M# W. Xversions of the standard system. The8 v) B0 _" E9 B1 s
example shows the layered approach6 b4 K9 _( A8 Y9 a2 q" q5 _
being applied to verify an individual! v- n# T: Z! f; d4 P9 K8 L+ `6 @
block as well as its integration into the
) B3 s, z1 V2 @/ Csubsystem and final system representation.

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2#
發表於 2009-5-7 06:27:58 | 只看該作者
有時候年紀大ㄉ工程師卻是很難溝通有時候年紀大ㄉ工程師卻是很難溝通有時候年紀大ㄉ工程師卻是很難溝通有時候年紀大ㄉ工程師卻是很難溝通

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