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A Layered Verification Approach Applied to an AMBA-Based System

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1#
發表於 2007-7-5 09:27:40 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
It’s common knowledge that the verification
4 x3 f; d( `& gstage for a given system is
$ t: S; ~) b6 w) [& S# Xaround 70% of the overall design8 d, t" c4 j# \: j1 Z
effort and schedule time. Reducing% d( {( Q! Q1 d
overall time spent in test creation and3 O* ^, a8 N) [! E$ N* A
design verification is a high priority.
( |) C" }- U; ^+ w# GSuccess in these two areas increases
1 e8 l8 o( ?! F9 \2 ~0 r: ?productivity and helps deliver products+ x5 L8 x. n! B& b, Z
to market faster. To achieve these verification
3 v3 _  u" n. @9 Ngoals, engineers are constantly
1 T4 B  b# E1 U! T+ ?0 klooking for new and innovative ways to
9 u# {' Z+ q! y( dconquer the verification challenges that7 Y& P1 H1 b+ y, Y# j
face them.
8 U% v) d3 S/ l, {This article discusses a layered verification
: p/ f6 s! ^4 V1 ]! Z$ W" Napproach as applied to an AMBAbased3 S+ O; w9 ~. I* T1 ?0 s3 I
system component. The layered: n: t4 D- b$ a2 Y
approach is used to create a standardized9 e& z( f- i/ |" Z+ G  b- d
verification environment that can9 k; N0 f/ x+ m- b" z# S  C
adapt as the design challenges
' ^% V1 n0 d4 g- h3 J- N! Q# xincrease. Typically, reuse is very high7 t- ~/ D3 a# o( ~; J
within an AMBA-based system because& a1 O) v) F* c- B( j2 D( w7 e5 G# s
many new designs are based on earlier9 t: B1 x% ]9 }7 H* b4 A- T
versions of the standard system. The5 ~4 p% q, c: S# z0 _. [( I
example shows the layered approach
8 j' |+ I8 }6 v- bbeing applied to verify an individual
3 h" y3 x8 {" E- Lblock as well as its integration into the* z% P) ?9 c/ k8 A! x0 S
subsystem and final system representation.

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2#
發表於 2009-5-7 06:27:58 | 只看該作者
有時候年紀大ㄉ工程師卻是很難溝通有時候年紀大ㄉ工程師卻是很難溝通有時候年紀大ㄉ工程師卻是很難溝通有時候年紀大ㄉ工程師卻是很難溝通

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