Time | Speech/
7 D. ?/ k0 g+ k0 f6 R9 C8 {, ]Platform | Topic | Speaker |
09:00~09:30 | Registration |
09:30~09:40 | Opening | Welcome Remark | Veronica Watson,
0 a0 W* I* U# C* q8 H+ x* GAP President of Cadence Design System' `, v9 h. `; X% h9 R* J
Willis Chang,
% c1 m. l2 S4 g& ~2 sCountry Manager of Cadence Taiwan r5 l) t* S; Y& I
|
09:40~10:10 | Keynote | EDA 360: The Way Forward for Electronic Design | Charlie Huang,
& F8 a1 l' u' t6 S+ g/ I; OSenior Vice President and
0 Q1 t- U+ F2 g! O+ `Chief Strategy Officer |
10:10~10:40 |
) A( S- M2 |- kKeynote | Cadence open integration platform with integration-optimized IP | Brian Gardner,
/ _3 ]! K9 l0 R0 xGroup Marketing Director, New Business, Cadence |
10:40~11:00 | Break (Proceed to Breakout Rooms) |
Custom Design
( Z4 N8 c# j9 h3 s# e, R# {(Meeting room A&B, 13F) |
11:00~11:50 | CD01 | TSMC AMS Reference Flow | M. J. Huang,
3 o, k0 o7 S3 K$ I) uTSMC |
11:50~13:30 | Lunch |
13:30~14:20 | CD02 | Virtuoso IC Design Platform 6.1.4 - Analog Design Exploration and Optimization | Alex Wang |
14:20~15:10 | CD03 | Virtuoso What's New 6.1.4 - Virtuoso Advancing the Art of Custom Design | Kevin Tsai |
15:10~15:40 | Break |
15:40~16:30 | CD04 | Advanced 32/28nm Node Challenges & Solutions - Enabling Fastest Time-to-Volume | Eason Lin |
Functional and System Verification
% v) N4 {2 \$ b" d" s(Ballroom C, 10F) |
11:00~11:50 | FV01 | Predictable System Realization | Michael McNamara |
11:50~13:30 | Lunch |
13:30~14:20 | FV02 |
; n# Q. k/ `( m/ p) ?8 q9 e7 HCadence TLM Design & Verification with C-to-Silicon Compiler | Mark Warren |
14:20~15:10 | FV03 | Cadence TLM to GDSII flow | Rich Owen |
15:10~15:40 | Break |
15:40~16:30 | FV04 | Cadence TLM Verification | Cadence Expert |
Digital Implementation ) G; ]3 D7 [* M6 T) @
(Ballroom A, 10F) |
11:00~11:50 | DI01 | Digital Implementation Update at TSMC Reference Flow 11 | Cadence Expert |
11:50~13:30 | Lunch |
13:30~14:20 | DI02 | DoT/MSoT for Mixed Signal Demo | Mladen Nizic |
14:20~15:10 | DI03 | EDI System Roadmap: Encounter Digital Implementation System - Enabling "More than Moore" | Wei Lii Tan |
15:10~15:40 | Break |
15:40~16:30 | DI04 | EDI System 9.1 Update | Cadence Expert |
Logic Design
8 h- m! z# S% d) |- f! v! `(Ballroom B, 10F) |
11:00~11:50 | LD01 | Cadence Logic Design Product Roadmap | Yoon Kim |
11:50~13:30 | Lunch |
13:30~14:20 | LD02 | Phyical Predictability in RTL Compiler Synthesis | Mark Ou |
14:20~15:10 | LD03 | Conformal ECO Designer | B. C. Shih |
15:10~15:40 | Break |
15:40~16:30 | LD04 | Can your spreadsheet do this ---- Innovative applications of pre-RTL chip planning | Anis Uzzaman |
System and IC Packaging
; q0 Y$ J$ w5 I(Meeting room C, 13F) |
11:00~11:50 | SPB01 | SiP and 3DIC/TSV Design in TSMC Reference Flow 11.0 | / Z1 M) d9 `( ^
Mike Peng, $ p0 ?/ e7 q" H( x6 H k5 o, ^
TSMC |
11:50~13:30 | Lunch |
13:30~14:20 | SPB02 | What's New Update for 16.3 Allegro Package Design and SI Simulation? | Joseph Kao
/ [' N* v- A( G3 |2 O9 ^" kThunder Lay |
14:20~15:10 | SPB03 | Distributed Co-design for IC-Package-Board | Thunder Lay |
15:10~15:40 | Break |
15:40~16:30 | SPB04 | Design issues from IC to package: Managing Package Outsourcing Engineering | Kevin Liu |
16:30~16:45 | Lucky Draw(Ballroom A, 10F) |
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