7/29 Cadence Tech Forum 2010

heavy91

  C2 _" K. }) S$ h5 XCadence益華電腦為電子設計產業提出設計的未來之路!  提供一個從設計開始到系統整合，適合於系統整合、應用開發與系統驗證的完整平台，這就是Cadence所勾勒出的EDA未來之路。EDA360願景能夠讓半導體公司建立威力強大的產品，讓消費性技術供應商能夠運用硬體、軟體與服務結合的生態系統，提供元件平台，能夠幫助公司具備更高競爭力與獲利力。

/ I. s: G# f3 U3 Z+ J　Cadence Tech Forum 2010讓所有電子產業設計專家能夠會見彼此，與Cadence益華電腦使用者、設計開發工程師， 和各業界專家一同討論，一同激勵電子設計產業的新願景。同時Cadence Tech Forum 2010亦提供了一個機會，了解 Cadence 益華電腦和其他友好夥伴共同開發的解決方案，與如何運用 Cadence益華電腦技術進行創新與研發。
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" Q$ G2 b. S1 q% h$ l　今年Cadence Tech Forum 2010活動議題涵蓋廣泛，其中包括幾個最令人矚目的話題: 低功耗設計、先進製程下的設計實現、正規驗證、 constraint-driven設計、系統封裝設計和電子系統層級設計等。

　歡迎參加Cadence Tech Forum 2010，讓你有機會更進一步了解Cadence益華電腦新的解決方法和產品特性，以及未來產品願景與策略。

heavy91

Time	Speech/ ; j/ d7 M, x; R. x9 @3 \; K) DPlatform	Topic	Speaker
09:00~09:30	Registration
09:30~09:40	Opening	Welcome Remark	Veronica Watson, 5 H8 T0 b1 j. I; ]* wAP President of Cadence Design System 7 j4 i. p/ L1 M6 [) {( tWillis Chang, 8 v1 v  ]  K2 ^9 h2 g; u' H' _2 i# H6 BCountry Manager of Cadence Taiwan 2 E! C; R7 O- h
09:40~10:10	Keynote	EDA 360: The Way Forward for Electronic Design	Charlie Huang, + h' K- Y0 L$ B9 x* R/ KSenior Vice President and Chief Strategy Officer
10:10~10:40	Keynote	Cadence open integration platform with integration-optimized IP	Brian Gardner, Group Marketing Director, New Business, Cadence
10:40~11:00	Break (Proceed to Breakout Rooms)
Custom Design ' i7 t3 h1 y0 N; J& W! q# z(Meeting room A&B, 13F)
11:00~11:50	CD01	TSMC AMS Reference Flow	M. J. Huang, # l! R/ G4 Z) z2 l' `; eTSMC
11:50~13:30	Lunch
13:30~14:20	CD02	Virtuoso IC Design Platform 6.1.4 - Analog Design Exploration and Optimization	Alex Wang
14:20~15:10	CD03	Virtuoso What's New 6.1.4 - Virtuoso Advancing the Art of Custom Design	Kevin Tsai
15:10~15:40	Break
15:40~16:30	CD04	Advanced 32/28nm Node Challenges & Solutions - Enabling Fastest Time-to-Volume	Eason Lin
Functional and System Verification , O/ {$ P+ A6 k( x(Ballroom C, 10F)
11:00~11:50	FV01	Predictable System Realization	Michael McNamara
11:50~13:30	Lunch
13:30~14:20	FV02	0 [  P. m/ @( u7 N' j) sCadence TLM Design & Verification with C-to-Silicon Compiler	Mark Warren
14:20~15:10	FV03	Cadence TLM to GDSII flow	Rich Owen
15:10~15:40	Break
15:40~16:30	FV04	Cadence TLM Verification	Cadence Expert
Digital Implementation ( `4 s! ~( l3 G# O* ?6 `(Ballroom A, 10F)
11:00~11:50	DI01	Digital Implementation Update at TSMC Reference Flow 11	Cadence Expert
11:50~13:30	Lunch
13:30~14:20	DI02	DoT/MSoT for Mixed Signal Demo	Mladen Nizic
14:20~15:10	DI03	EDI System Roadmap: Encounter Digital Implementation System - Enabling "More than Moore"	Wei Lii Tan
15:10~15:40	Break
15:40~16:30	DI04	EDI System 9.1 Update	Cadence Expert
Logic Design 6 @3 ?3 d, z) E" [+ z8 H; Q1 s$ ^(Ballroom B, 10F)
11:00~11:50	LD01	Cadence Logic Design Product Roadmap	Yoon Kim
11:50~13:30	Lunch
13:30~14:20	LD02	Phyical Predictability in RTL Compiler Synthesis	Mark Ou
14:20~15:10	LD03	Conformal ECO Designer	B. C. Shih
15:10~15:40	Break
15:40~16:30	LD04	Can your spreadsheet do this ---- Innovative applications of pre-RTL chip planning	Anis Uzzaman
System and IC Packaging (Meeting room C, 13F)
11:00~11:50	SPB01	SiP and 3DIC/TSV Design in TSMC Reference Flow 11.0	2 H6 J/ p' ~- gMike Peng, 3 A5 K% x* h9 V6 F) ETSMC
11:50~13:30	Lunch
13:30~14:20	SPB02	What's New Update for 16.3 Allegro Package Design and SI Simulation?	Joseph Kao ; X, F4 k# k; K0 y- }. o; hThunder Lay
14:20~15:10	SPB03	Distributed Co-design for IC-Package-Board	Thunder Lay
15:10~15:40	Break
15:40~16:30	SPB04	Design issues from IC to package: Managing Package Outsourcing Engineering	Kevin Liu
16:30~16:45	Lucky Draw(Ballroom A, 10F)
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