Month
# X& N- a" ^! r+ a' h- z | Topic
2 |) f, S' e! U$ |; `8 T |
January9 y% ^( N% X# n) r. O
| • Parasitics & Parasitic Extraction! n+ K. m! U( m: o
|
February/ N) ~2 P7 e6 w. C
| • Verification Methodologies & Tools
9 _2 B, L9 e: o• CAE/CAD Tools for FPGAs
* F3 [! l5 H+ b; q7 r1 r( a |
March+ c: o; N' b$ n# O1 |2 ?
| • Configurable & Reconfigurable Processors
4 @0 A* A' X; c, [! h |
April2 f- h2 `2 x' j F) I% C1 b# ]
| • Hardware/Software Co-Design
- K! O2 i' v4 J1 r7 C• On-chip Interconnect, Network on chip (NoC) # a+ i( {4 O8 [
|
May
! k) h" M$ [; N | • Electronic System Level Design (ESL)
, O& C% n+ c9 U2 q2 U1 }# ? |
June- {4 l0 b8 ?# s* Y; }, S
| • Timing Analysis, Closure, & Sign-off" P6 A* I! V+ {
• Low-power Design Methodologies & Tools
$ c) l: c# w9 H3 E, h |
July
9 N7 o% t0 ]5 _5 P7 [5 Z L | • FPGAs in DSP Applications
4 @2 P/ `6 r* G5 X o |
August9 j J+ V+ f, ~% _
| • Formal Verification Methodologies & Tools7 q G* u+ `* F% [* u8 E7 O/ A) ]
|
September
( p* f" `! h/ G | • Structured ASICs & FPGA-to-ASIC Conversion
' V: z3 Q, `' `• Design-for Manufacturing/Yield (DFM & DFY)
6 \- f8 H# M a/ y, P* i3 u5 |: I |
October, ?3 \$ y" F6 w; A" Q0 d
| • ATPG, BIST & DFT
: r5 n& A$ B2 R# L$ e |
November# ?3 U/ {& e) L' z$ q: W& C; Y
| • Physical Design (Partitioning, Floorplanning & Placement, Routing, Optimization)
( [: p" v8 I0 @3 |• Device/Circuit Modeling & Simulation
' E7 k% R& B' b+ o |
December
7 |. j: q' a' G5 H, P7 x5 \/ L7 V | • Analog & Mixed-Signal Design2 Q# ?+ l+ ^: N
|