Month* k( B: m! h, Y; M) `
| Topic) O6 f1 d) i2 D- \' R/ ^
|
January
5 @4 v. h8 k& G | • Parasitics & Parasitic Extraction
1 w$ O4 ~* O2 w7 `/ }$ y |
February
% d: j* r/ ]( t" x | • Verification Methodologies & Tools
- T: h b8 L( E k4 W* G• CAE/CAD Tools for FPGAs; ~. e$ S8 V. N( d7 l; r$ ~( l
|
March
: l! q' J+ R, l' P# Z2 D1 X- g! Q | • Configurable & Reconfigurable Processors
, I G$ V1 ^$ G |
April
, N" z U/ O1 F: N9 J | • Hardware/Software Co-Design2 g" W6 T% D9 r1 z
• On-chip Interconnect, Network on chip (NoC)
+ Y# D" G8 `/ Z$ g8 T6 x |
May
3 f; _% D; {& Z0 E; l) m; \2 @# Z0 Z | • Electronic System Level Design (ESL)0 }0 P5 D( x- b1 s$ z: H8 i
|
June
o! Q* A3 y, w4 D | • Timing Analysis, Closure, & Sign-off
2 j3 b& X1 u9 `! ~• Low-power Design Methodologies & Tools6 @5 R1 H: S5 J, `9 l! d/ k
|
July' f5 N1 E8 J: L) U# d
| • FPGAs in DSP Applications
6 F0 v( a) o! c$ i# E! ]# b$ @ |
August2 q O3 m8 R4 x! c- U. V- ?
| • Formal Verification Methodologies & Tools
3 O( x$ x7 c# f3 K |
September. d P7 Y; E: \7 R/ P
| • Structured ASICs & FPGA-to-ASIC Conversion
! Y7 ~: g7 B& I• Design-for Manufacturing/Yield (DFM & DFY) ' M& _" G8 c& K1 w5 c
|
October
7 U. j6 I- h# P* ] | • ATPG, BIST & DFT5 D' w4 D7 m; c' A$ M
|
November( G- o8 M" F& j8 c
| • Physical Design (Partitioning, Floorplanning & Placement, Routing, Optimization)% D% }* i7 V( d
• Device/Circuit Modeling & Simulation
- B1 f# h1 @' m' B |
December
6 z5 k! j0 }$ j7 a, b | • Analog & Mixed-Signal Design
0 E `& X" \, ] @' u8 Q |