靜電放電測試

ritafung

剛剛研究了靜電放電（ HBM ＆ MM） JEDEC標準，實在需要很長的時間去進行測試。假設該IC具有數以百計的pin，很可能將需要超過1個月完成整個測試。這裡是否有任何人負責做ESD測試？

m851055

竹科閎康科技有此業務
電話在網頁就查的到了.......................

cuban487

很多實驗室好像都有,但都在台北.
儀特好像就有可以去查ㄧ下

kyyyyyykimo

目前新竹地區有"宜特"與"閎康"兩家比較大
$ R& w' o/ o5 {' _* B6 j1 W我的建議是去閎康，會比較適合。
; ^% X' k. ^; o5 L' \因為我本身工作性質也是有接觸到ESD測試
測試多Pin需要花費時間比較長久，可是你們HBM是使用JECDE
( l5 Y# t# f! x0 ?  B3 V在Zap的次數明顯比軍歸來的少了。
! s) k, Q+ I" x

ritafung

my company is pursuading to MIL-Std ...
" V% L7 G4 g+ y6 Z5 \, [actually any company need MIL-Std? Our application is not for military purpose....

wesleysungisme

For ESD test (HBM)
The following are the test combination:
% ?) K* _6 m/ E1. Power to Power
2. Power to Ground
) A5 Q- _! `: b3. IO to Power
% U. M7 Y/ t' o! G4. Io to Ground
2 `9 }+ G% u' s& |4 E- X8 s2 }5. IO to IO
(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.)
3 b: O9 q  ]* R4 X* g; N# O7 r
( G" P( I' |, L4 T7 I2 Q- ~  Qthe total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG)
! `- Q. d% d  x7 R- a7 @  u+ e0 SFor example: You have IO1/IO2/IO3/P1/P2/G1
2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)
So for high pin count it will take a lot of time. But it won't take more than a week(for one chip).

2 |: w: Q, w$ M! L- |For your reference.

f5882077

樓上的Jason...據我所知大部分的IC設計都會跑去宜特做ESD...為什麼你要特別建議去閎康做呢??
有什特殊原因嗎??會比較適合的邏輯是什麼??是否可分享一下心得??感恩~

ritafung

thanks wesleysungisme for your answer.
as our pin count is over 1000 and no. of power is ~ 20, so it's quite time-consuming.
and there is technical issue about bonding all the dies into COB for ESD zapping, i wonder if anyone could share their practise? we feel difficult to strictly follow JEDEC standard.