靜電放電測試

ritafung

剛剛研究了靜電放電（ HBM ＆ MM） JEDEC標準，實在需要很長的時間去進行測試。假設該IC具有數以百計的pin，很可能將需要超過1個月完成整個測試。這裡是否有任何人負責做ESD測試？

m851055

竹科閎康科技有此業務
電話在網頁就查的到了.......................

cuban487

很多實驗室好像都有,但都在台北.
5 z6 z8 w5 L6 d3 M( Z儀特好像就有可以去查ㄧ下

kyyyyyykimo

目前新竹地區有"宜特"與"閎康"兩家比較大
8 o4 I; D7 i7 v! A) l& ?( |我的建議是去閎康，會比較適合。
因為我本身工作性質也是有接觸到ESD測試
* t7 i' {# i1 X- P- t% i( ]測試多Pin需要花費時間比較長久，可是你們HBM是使用JECDE
在Zap的次數明顯比軍歸來的少了。

ritafung

my company is pursuading to MIL-Std ...
actually any company need MIL-Std? Our application is not for military purpose....

wesleysungisme

For ESD test (HBM)
9 V5 m* u1 W( r3 k3 V; k8 nThe following are the test combination:
7 r/ _, n4 g# J$ h& E. z1. Power to Power
% i* g* ?. l& Y2 Z0 b3 n$ ^* u4 A$ c2. Power to Ground
$ }+ Q& V2 K3 s, a8 J4 \$ r3 T3. IO to Power
' j9 T0 ?% v4 M4. Io to Ground
: f  \" G4 v5 q+ t& Y' q8 n5. IO to IO
1 @0 {0 c8 w( f" [(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.)
0 Z5 [( Y7 P$ u* i, Q/ u- |. a
) v6 ^) x: E6 nthe total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG)
5 p+ d9 s: [2 t, t) [For example: You have IO1/IO2/IO3/P1/P2/G1
2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)
So for high pin count it will take a lot of time. But it won't take more than a week(for one chip).

For your reference.

f5882077

樓上的Jason...據我所知大部分的IC設計都會跑去宜特做ESD...為什麼你要特別建議去閎康做呢??
有什特殊原因嗎??會比較適合的邏輯是什麼??是否可分享一下心得??感恩~

ritafung

thanks wesleysungisme for your answer.
' U4 g! U8 c; x- Sas our pin count is over 1000 and no. of power is ~ 20, so it's quite time-consuming.
  h# A0 n8 E4 k, p* p& V. wand there is technical issue about bonding all the dies into COB for ESD zapping, i wonder if anyone could share their practise? we feel difficult to strictly follow JEDEC standard.